• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.25 no.4
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• pp.393-400
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• 2014

In this paper, we have designed the transmitter for earth station terminal operating with military geostationary satellite on Ka-band that is complied with MIL-STD-188-164A. The designed antenna of this terminal is dual-offset gregorian reflector which is consist of corrugated horn and iris polarizer, othermode transducer. This antenna meets radiation pattern and transmit EIRP spectral density requirements in this standard. The designed RF systems of this terminal are consist of Block Up Converter(BUC) converting frequency band from IF to Ka band and SSPA having low-power consumption and compact light-weight using the pHEMT MMIC compound devices. This RF systems applied with VSWR, spurious/harmonic suppression, output flatness and phase noise requirement in this standard.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.16 no.8
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• pp.1734-1740
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• 2012

In this paper, we propose a FSOURCE circuit which requires such a small switching current that an eFuse OTP memory can be programmed in the post-package state of the PMIC chips using a single power supply. The proposed FSOURCE circuit removes its short-circuit current by using a non-overlapped clock and reduces its maximum current by reducing the turned-on slope of its driving transistor. Also, we propose a DOUT buffer circuit initializing the output data of the eFuse OTP memory with arbitrary data during the power-on reset mode. We design a 24-bit differential paired eFuse OTP memory which uses Magnachip's $0.35{\mu}m$ BCD process, and the layout size is $381.575{\mu}m{\times}354.375{\mu}m$($=0.135mm^2$).

• The Journal of Information Technology
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• v.4 no.3
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• pp.77-86
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• 2001

In this paper, Electromagnetic scattering problem by a resistive strip grating with 2 dielectric layers on a ground plane according as resistivity of resistive strip, relative permittivity and thickness of dielectric layers, and incident angles of a electric wave is analyzed by applying the PMM (Point Matching Method) known as a numerical procedure. The scattered electromagnetic fields are expanded in a series of floquet mode functions. The boundary conditions are applied to obtain the unknown field coefficients and the resistive boundary condition is used for the relationship between the tangential electric field and the electric current density on the strip. According as the relative permittivity and the thickness of layers are increased, the values of the geometrically normalized reflected power have a high value and the values of strip width are moved toward a high value going from left to right. When the resistivity of this paper has a value of zero, the numerical results of the geometrically normalized reflected power show in good agreement with those by the PMM of existing paper. Then, the most energys of the sharp variation point in minimum values of the geometrically normalized reflected power are scattered in direction of the other angles except incident angle.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.37 no.4
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• pp.28-34
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• 2000

In this paper, a continuous-time filter for low voltage and high frequency applications using fully-balanced current integrators is presented. As the balanced structure of integrator circuits, the designed filter has improved noise characteristics and wide dynamic range since even-order harmonics are cancelled and the input signal range is doubled. Using complementary current mirrors, bias circuits are simplified and the cutoff frequency of filters can be controlled easily by a single DC bias current. As a design example, the 3rd-order lowpass Butterworth filter with a leapfrog realization is designed. The designed fully-balanced current-mode filter is simulated and examined by SPICE using 0.65${\mu}{\textrm}{m}$ CMOS n-well process parameters. The simulation results show 50MHz cutoff frequency, 69㏈ dynamic range with 1% total harmonic distortion(THD), and 4㎽ power dissipation with a 3V supply voltage.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.39 no.4
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• pp.25-35
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• 2002

This work describes an 8b 200MHz time-interleaved subranging analog-to-digital converter (ADC) based on a single-poly digital CMOS process. Two fine ADCs for lower digital bits of the proposed ADC employ a time-sharing double-channel architecture to increase system speed and a new reference voltage switching scheme to reduce settling time of the reference voltages and chip area. The proposed intermeshed resistor string, which generates reference voltages for fine ADCs, improves linearity and settling time of the reference voltages simultaneously. The proposed sample- and-hold amplifier(SHA) is based on a highly linear common-drain amplifier and passive differential circuits to minimize power consumption and chip area with 8b accuracy and employs input dynamic common mode feedback circuits for high dynamic performance at a 200MHz sampling rate. A new encoding circuit in a coarse ADC simplifies the signal processing between the coarse ADC and two successive fine ADCs.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.40 no.4
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• pp.85-94
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• 2003

The asynchronous design methods proved to have the higher performance in power consumption and execution speed than synchronous ones because it just needs to activate the required module without feeding clock in the system. Despite the advantage of CISC machine providing the variable addressing modes and instructions, its execution scheme is hardly suited for a synchronous Pipeline architecture and incurs a lot of overhead. This paper proposes a novel asynchronous pipeline architecture, A80sl, whose instruction set is fully compatible with that of Intel 80C51, an embedded micro controller. We classify the instructions into the group keeping the same execution scheme for the asynchronous pipeline and optimize it eliminating the bubble stage that comes from the overhead of the multi-cycle execution. The new methodologies for branch and various instruction lengths are suggested to minimize the number of states required for instructions execution and to increase its parallelism. The proposed A80C51 architecture is synthesized with 0.35${\mu}{\textrm}{m}$ CMOS standard cell library. The simulation results show higher speed than that of Intel 80C51 with 36 MHz and other asynchronous counterparts by 24 times.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.39 no.4
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• pp.93-103
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• 2002

A new current mirror for high-accuracy current-mode signal processing and integrated circuit design was proposed. The current mirror adopts the technique of an adaptive feedback to reduce the input impedance and the output stage of regulated cascode current mirror to increase the output impedance. Simulation results show that the current mirror has input impedance of 0.9Ω, the output impedance of 415 MΩ, and current gain of 0.96 at the supply voltage Vcc=5V. The power dissipation is 1.5㎽. In order to certify the applicability of the proposed current mirror, a voltage-to-current converter using the current mirror is designed. Simulation results show that the converter has good agreement with theoretical equation and has three times better conversion characteristics when compared with voltage-to-current converter using Wilson current mirror.

• Journal of the Korean Institute of Telematics and Electronics D
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• v.36D no.5
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• pp.69-79
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• 1999

In this paper, we proposed a diffuion model of Ti diffused lithium niobate optical waveguide for fabricating waveguides with high refractive index and compared with conventional one. The achivement of low optical insertion loss between waveguide interface and single mode fibers was discussed as a function of Ti thickness for $\lambda$=1.55$\mu\textrm{m}$ The proposed diffusion method exhibited higher refractive index waveguide than conventional one for $\lambda$=0.6328$\mu\textrm{m}$ We have achieved the total fiber-waveguide-fiber insertion loss as low as 0.5dB/cm in z-cut and 1$\pm$0.5dB/cm in x-cut for both TM and TE mode of Mach-Zehnder interferometric waveguide in the range of Ti thickness 1000-1400$\AA$ for $\lambda$=1.55$\mu\textrm{m}$ From these results, this diffusion model for making a low loss waveguide can be used for low-power-modulators and switches.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.12
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• pp.30-35
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• 2009

In this paper, we propose the flexible design architecture for a continuous packet connectivity (CPC) Protocol among additional features of 3GPP HSPA+. In order to meet a practical intellectual property (IP) reuse and the developing time reduction design goals, we utterly take a CPC protocol into account to be realized by reusing digital signal processor (DSP) IP of the proven high speed packet access (HSPA) platform with the minimum hardware modification and addition. Based on the Teak series DSP, the proposed CPC protocol is divided into discontinuous transmit and receive mode, CPC manager, and interface with the proven HSPA platform. According to the regularized verification flow for wireless cellular communication applications, the proposed CPC protocol has been verified in various test scenarios.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.38 no.10
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• pp.754-764
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• 2001

Class A bipolar second-generation current conveyor (CCII) with low current-input impedance and its offset-compensated CCII for high-accuracy current-mode signal processing are proposed. The CCIIs consist of a regulated current-cell for current input, a emitter follower for voltage input, and a cascode current mirror lot current output. In these architecture, the two input stages are coupled by current mirror to reduce the current input impedance. Experiments show that the CCII has impedance of 8.4 Ω and offset voltage of 40 mV at current input terminal. To reduce this offset, the offset-compensated CCII adopts diode-connected npn and pnp transistor in the proposed CCII. Experiments show that the offset-compensated CCII has current input impedance of 2.1 Ω and offset voltage of 0.05 mV. The 3-dB cutoff frequency of the CCIIs when used as a voltage follower extends beyond 30 MHz. The power dissipation is 7.0 mW