• Journal of Navigation and Port Research
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• v.26 no.3
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• pp.295-302
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• 2002

Currently digital communication system adapt various digital modulation schemes. All these communication systems are required to cause the minimum interference to adjacent channels, they must therefore employ the linear power amplifiers. In respect to linear power amplifiers, there are many linearization techniques. Feedforward power amplifier represent very wide bandwidth and high linearization capability. In the feedforward systems overall efficiency is reduced due to the loss of delay line. In this paper, delay filter instead of transmission delay line adapted to get more high efficiency. Experimental results showed that ACLR has improved 17.04dB which is added 2.54dB by using the delay filter.

• Proceedings of the Korean Society of Marine Engineers Conference
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• 2006.06a
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• pp.301-302
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• 2006

초고주파 전력 증폭기의 바이어스 전압을 조절하여 온도 변화에 따른 드레인(Drain) 전류의 변화를 억제하기 위한 저가의 능동 바이어스 모듈을 개발한다. 능동 바이어스 모듈을 5 W급 초고주파 전력증폭기에 적용하였을 경우, $0{\sim}60^{\circ}C$까지의 온도변화에 대하여 소모전류 변화량은 0.1 A 이하로 되어야 한다. 본 기술 개발 대상인 능동 바이어스 모듈의 성능 시험을 위한 대상 전력증폭기는 $2.11{\sim}2.17GHz$ 주파수 대역에서 32 dB 이상의 이득과 ${\pm}0.1\;dB$ 이하의 이득 평탄도, -15 dB 이하의 입.출력 반사손실을 가진다.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.43 no.5 s.347
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• pp.128-136
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• 2006

In this paper, design and implement 50W Doherty power amplifiers for 3GPP repeater and base station transceiver system. Efficiency improvement and high power property of ideal Doherty power amplifier is distinguishable; however bias control for implementation of Doherty(GDCHD) amplifier is difficult. To solve the problem, therefore, GDCHD(Gate and Drain Control Hybrid Doherty) power amplifier is embodied to drain bias adjustment circuit to Doherty power amplifier with gate bias adjustment circuit. Experiment result shows that $2.11{\sim}2.17\;GHz$, 3GPP operating frequency band, with 57.03 dB gain, PEP output is 50.30 dBm, W-CDMA average power is 47.01 dBm, and -40.45 dBc ACLR characteristic in 5MHz offset frequency band. Each of the parameter satisfied amplifier specification which we want to design. Especially, GDCHD power amplifier shows proper efficiency performance improvement in uniformity ACLR than Doherty power amplifier.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2015.05a
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• pp.681-684
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• 2015

Power amplifier is an essential component for transmitting signals to a remote receiver in wireless communication systems. Power amplifier is a non-linear device in general, and the nonlinear distortion becomes severer as the output power increases. The nonlinearity results in spectral regrowth, which leads to adjacent channel interference, and decreases the transmit signal quality. To linearize power amplifiers, many techniques have been developed so far. Among the techniques, digital pre-distortion is known as the most cost and performance effective technique. However, the linearization performance falls down abruptly when the power amplifier operates in its saturation region. This is because of the severe nonlinearity. To relieve this problem, this paper proposes a new adaptive predistortion technique. The proposed technique controls the adaptive algorithm based on the power amplifier input level. Specifically, for small signals, the adaptive predistortion algorithm works normally. On the contrary, for large signals, the adaptive algorithm stops until small signals occur again. By doing this, wrong coefficient update by severe nonlinearity can be avoided. Computer simulation results show that the proposed method can improve the linearization performance compared with the conventional digital predistortion algorithms.

• Journal of the Institute of Electronics and Information Engineers
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• v.51 no.4
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• pp.59-65
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• 2014

In this paper, in order to improve efficiency performance of power amplifiers, a mode changeable autotransformer is proposed. Efficiency performance at the low-power mode can be improved by adopting the mode changeable autotransformer. A dual-mode autotransfomrer CMOS power amplifier using a standard 0.18-${\mu}m$ CMOS process is designed in this work. Number of turns in a primary winding is re-configurated according to mode change between the high-power mode and the low-power mode. Thus, the efficiency performance of the power amplifier at each mode is optimized. EM and total circuit simulation results verify that low-power mode power added efficiency(PAE) at 24dBm output power is improved from 10.4% to 26.1% using the proposed multi-mode operation.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.10 no.5
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• pp.947-954
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• 2009

This paper proposed a new balanced power amplifier using the reflected input of conventional balanced power amplifiers composed of branch line hybrid coupler. In general, the single-ended amplifier in balanced amplifiers does not have the perfect matching, so the reflected input power, in other words the leakage power, is terminated conventionally at the isolation port of hybrid coupler. However in this work, the leakage power is injected into the auxiliary amplifier, and its output power is combined to the output power of balanced amplifier. Therefore output power, efficiency, and 2-tone IMD3 performances of the proposed balanced amplifier are highly improved compared to the conventional balanced amplifier. For the verification of the proposed balanced amplifier, a conventional balanced amplifier and the proposed balanced amplifier are designed, fabricated and measured, and the measured results are compared. The proposed balanced amplifier shows the improvement in the output power(Pout), power added efficiency (PAE), and 2-tone IMD3 by 3dB, 5.2%, and $5{\sim}10dBc$, respectively, from the measurement.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.28 no.6
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• pp.435-443
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• 2017

In this study, we analyzed the effects of the common-gate transistor bias of a switching mode CMOS power amplifier. Although the most earier works occured on the transistor sizes of the cascode structure, we showed that the gate bias of the common-gate transistor also influences the overall efficiency of the power amplifier. To investigate the effect of the gate bias, we analyzed the DC power consumption according to the gate bias and hence the efficiency of the power amplifier. From the analyzed results, the optimized gate bias for the maximum efficiency is lower than the supply voltage of the power amplifier. We also found that an excessively low gate bias may degrade the output power and efficiency owing to the effects of the on-resistance of the cascode structure. To verify the analyzed results, we designed a 1.9 GHz switching mode power amplifier using $0.18{\mu}m$ RF CMOS technology. As predicted in the analysis, the maximum efficiency is obtained at 2.5 V, while the supply voltage of power amplifier is 3.3 V. The measured maximum efficiency is 31.5 % with an output power of 29.1 dBm. From the measureed results, we successfully verified the analysis.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.13 no.2
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• pp.146-154
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• 2002

This paper presents a linearization technique up to the saturation region of power amplifiers. The predistorter gain polynomials which have optimum coefficients are introduced. Power amplifiers are most efficient when operated near the saturation region. Compensating the amplifier nonlinearities with these predistorter gain polynomials, the efficiency of the amplifier can be maximized. Simulation results demonstrate that the adjacent channel power ratio (ACPR) is improves by about 63 ㏈ at the band edge. The convergence and reconvergence characteristics of the linearizer are also satisfactory.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.10 no.11
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• pp.1934-1939
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• 2006

Current digital communication system is selecting very various digital Modulation way. Need linear power amplifier necessarily to reduce interference for contiguity channel maximum in this communication system and at the same time, power amplifier of high efficiency is required. In this paper Compare with result of equilibrium power amplifier that design Doherty power amplifier of way that linearity and efficiency are improved at the same time through simulation optimization techniques and at the same time design through simulation, efficiency 20% linearity showed 10dB that is improved.

• The Journal of The Korea Institute of Intelligent Transport Systems
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• v.9 no.2
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• pp.51-59
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• 2010

In this paper, we propose an inverted type asymmetric Doherty amplifier with optimized efficiency characteristic in wanted output power back-off (OPBO) range according to peak to average power ratio of input signal In order to obtain optimized efficiency of the asymmetric Doherty amplifier in wanted OPBO, peak power ratio between main amplifier and peaking amplifier was determined and then impedance of 90 degrees impedance transformer was obtained by peak power ratio. The offset line length and peak dividing ratio of the asymmetric Doherty amplifier were also calculated. From the measurement results, the proposed amplifier has achieved 40 % drain efficiency and -35 dBc adjacent channel leakage ratio at the average output power of 48.7 dBm for CDMA 2000 1x 3-FA test signal.