• The KIPS Transactions:PartA
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• v.13A no.3 s.100
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• pp.191-198
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• 2006

Today's portable electric consumer devices, which are operated by battery, tend to integrate more multimedia processing capabilities. In the multimedia processing devices, multimedia system-on-chips can handle specific algorithms which need intensive processing capabilities and significant power consumption. As a result, the power-efficiency of multimedia processing devices becomes important increasingly. In this paper, we propose a reconfigurable data caching architecture, in which data allocation is constrained by software support, and evaluate its performance and power efficiency. Comparing with conventional cache architectures, power consumption can be reduced significantly, while miss rate of the proposed architecture is very similar to that of the conventional caches. The reduction of power consumption for the reconfigurable data cache architecture shows 33.2%, 53.3%, and 70.4%, when compared with direct-mapped, 2-way, and 4-way caches respectively.

• Journal of Korea Society of Industrial Information Systems
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• v.28 no.1
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• pp.17-25
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• 2023

As the range of use of urban unmanned aerial vehicles (UAV) expands, it is necessary to operate UAVs efficiently because of its limited battery capacity. For this, it is required to find the optimal flight profile with various simulations. Therefore, it is important to predict the power and energy consumption of the UAV battery. In this paper, we analyzed the relationship between the speed and acceleration of the UAV and power consumption during the flight. Then, we derived a linear model, which is easily utilized. In addition, we also derived an accurate power consumption model based on deep neural network learning. To find the efficient model, we used learning data as 1) the GPS 3-axis velocity and acceleration data, 2) the IMU 3-axis velocity only, and 3) the IMU 3-axis velocity and acceleration data. The final model shows 5.86% error rate for power consumption and 1.50% error rate for the cumulative energy consumption.

• 한국ITS학회:학술대회논문집
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• 2008.11a
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• pp.154-157
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• 2008

유비쿼터스 센서 네트워크에서 전력 효율을 높이는 것은 매우 중요한 과제이다. 노드의 전력 소비를 줄이기 위해 다양한 mac protocol 들이 제안되어 왔고, 본 논문에서는 ns2(network simulator) tool을 이용하여 Wei Ye, John Heidemann, Deborah Estrin 이 2002년에 발표한 S-MAC Protocol 의 전력효율을 기존의 IEEE 802.11 MAC 과 비교하였다.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.21 no.5
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• pp.59-69
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• 2011

Since power analysis attack which uses a characteristic that power consumed by crypto device depends on processed data has been proposed, many logics that can block these correlation originally have been developed. DRP logic has been adopted by most of logics maintains power consumption balanced and reduces correlation between processed data and power consumption. However, semi-custom design is necessary because recently design circuits become more complex than before. This design method causes unbalanced design pattern that makes DRP logic consumes unbalanced power consumption which is vulnerable to power analysis attack. In this paper, we have developed new logic style which adds another discharge phase to discharge two output nodes at the same time based on DyCML to remove this unbalanced power consumption. Also, we simulated 1bit fulladder to compare proposed logic with other logics to prove improved performance. As a result, proposed logic is improved NED and NSD to 60% and power consumption reduces about 55% than any other logics.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.5
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• pp.16-23
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• 2010

This paper presents 6bit 250MS/s flash A/D converter which can be applied to wireless communication system. To solve the problem of large power consumption in flash A/D converter, control algorithm by input signal level is used in comparator stage. Also, input voltage range detector circuit is used in reference resistor array to minimize the dynamic power consumption in the comparator. Compared with the conventional A/D converter, the proposed A/D converter shows 4.3% increase of power consumption in analog and a seventh power consumption in digital, which leads to a half of power consumption in total. The A/D converter is implemented in a $0.18{\mu}m$ CMOS 1-poly 6-metal technology. The measured results show 106mW power dissipation with 1.8V supply voltage. It shows 4.1bit ENOB at sampling frequency 250MHz and 30.27MHz input frequency.

• Proceedings of the Korea Information Processing Society Conference
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• 2016.04a
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• pp.903-906
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• 2016

최근 사물인터넷(IoT, Internet of Things)관련 기술의 발전 및 서비스 산업의 급속한 발전으로 센서 장치에 대한 수요가 증가하고 있다. 센서 장치는 사물인터넷 플랫폼과의 연동을 위한 통신 인터페이스를 필수로 지원하여야 하며, 그 외에 다양한 센서들의 연동 인터페이스와 소비 전력을 모두 고려하여 하드웨어 및 소프트웨어의 설계가 이루어져야 한다. 이와 같이 센서 장치는 베터리 소비를 최적화하여 모든 기능이 구현되어야 하므로 기능상의 제약이 많이 따른다. 시간 동기화를 위해 사물인터넷 플랫폼에서 송신하는 동기 메시지를 수신하기 위해 슬립모드를 지원하는 경우 센서 장치가 항상 깨어 있어야하므로 저전력으로 동작 할 수 없는 어려움이 따른다. 따라서 데이터를 센싱하는 주기에 맞춰 시간 동기화를 진행하는 프로토콜 및 지연 시간 계산 방안을 제시하고 이에 따른 기존 프로토콜들과 비교하여 경량화한 알고리즘을 제안한다. 향후 시간 동기화 프로토콜의 호환을 위해 CoAP 규격과 연동 될 수 있는 연구가 필요하다.

• Journal of Sensor Science and Technology
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• v.6 no.2
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• pp.137-144
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• 1997

In this paper, the design of a 10-bit 40-MS/s pipelined A/D converter is implemented to achieve low static power dissipation of 70 mW at the ${\pm}2.5\;V$ or +5 V power supply environment for high speed applications. A 1.5 b/stage pipeline architecture in the proposed ADC is used to allow large correction range for comparator offset and perform the fast interstage signal processing. According to necessity of high-performance op amps for design of the ADC, the new op amp with gain boosting based on a typical folded-cascode architecture is designed by using SAPICE that is an automatic design tool of op amps based on circuit simulation. A dynamic comparator with a capacitive reference voltage divider that consumes nearly no static power for this low power ADC was adopted. The ADC implemented using a $1.0{\mu}m$ n-well CMOS technology exhibits a DNL of ${\pm}0.6$ LSB, INL of +1/-0.75 LSB and SNDR of 56.3 dB for 9.97 MHz input while sampling at 40 MHz.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2012.10a
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• pp.765-768
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• 2012

Recently, the supply ratio of smart devices application has become increasable, utilization of device increases constantly. At the same time, used application is more gentrified. However, using time of devices is decreased. To solve these problems, many research is studying about the hardware/software. One of them is profiling power consumption by process units. The process can be managed, based on measured energy consumption data. These means that it can efficiently use the residual energy. Application at the stage of program design can analyze and used-energy using the trace by considering the low-power can design. In this paper, we studied software-based power-metering framework for android platform. We survey each process-level power consumption measurement techniques, compare advantages and disadvantages of the technique and propose improved measures.

• The KIPS Transactions:PartC
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• v.11C no.4
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• pp.555-562
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• 2004

We consider differentiated bandwidth allocation for a piconet in short-range wireless personal network systems : Bluetooth. Since bandwidth requirements nay vary among applications/services, and/or it may change over time, it is important to decide how to allocate limited resources to various service classes to meet their service requirements. We propose a simple and efficient bandwidth allocation mechanism which meets bandwidth requirements of various service types while saving power consumption by a Power saying mode, i.e., sniff node. We compare our proposed mechanism with a conventional (weighted) round-robin polling scheme and show that it achieves significant improvement of hroughput, delay, and power consumption.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.14 no.2
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• pp.437-444
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• 2010

The audio data have been communicated using analog methods or simple protocols. However, with the advent and improvement of various multimedia functions, many audio devices have been integrated into a mobile handset in which interconnection lines are very complicated. Conventional point-to-point connections such as $I^2S$ and PCM demand more power consumption whenever more devices are attached. In this paper, we design a common bus digital audio interface that communicates with only two wires and employs the clock gear method to reduce bus power consumption. The comparison results show that the proposed common bus connection can reduce more than 30% of power consumption as compared with point-to-point connection if more than three devices are connected.