• Proceedings of the Korean Information Science Society Conference
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• 2002.10e
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• pp.274-276
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• 2002

Ad Hoc망은 전형적인 무선 네트워킹과는 다른 새로운 무선 네트워킹 파라다임으로써 기존 유선 망의 하부 구조에 의존하지 않고 이동 호스트들로만 구성된 네트워크이다. Ad Hoc망에서 통신을 하기 위해서는 출발지 노드에서 목적지 노드까지 데이터 전송을 위한 라우팅에 관한 문제이다. Ad Hoc망에서는 모든 단말기의 위치변화가 가능하기 때문에 경로설정에 어려움이 따른다. 노드간에 정보를 보내고자 할 때 노드가 인접한 상태가 아니면 정보를 직접 보낼 수 없고 여러 중간 노드들을 거쳐서 정보를 보내는 다중-홉 라우팅 방식을 사용해야 한다. 따라서 중간 노드들은 패킷 라우터의 역할을 해야하는데 무선 통신자체가 좁은 대역폭과 한정된 채널을 가지고 전송 범위가 제한되는 문제가 있다. 또한 노드자체의 이동성과 전력 소모 등으로 인한 이탈은 망 위상을 수시로 변화시키므로 노드간에 정보를 전송하는데 가장 좋은 경로는 수시로 변경될 수 있으므로 많은 어려움이 따르게 된다. 본 논문에서는 이러한 문제의 해결방안으로 경로유지 과정에서 Ad Hoc망 내의 노드들은 이동성의 특성으로 인해 현재 사용되는 경로 보다 더 짧고 효율적인 경로가 발생하고 중간 노드가 이동 될 때 새로운 경로로 갱신하여 솔기없는 최적의 경로를 유지할 수 있는 방법을 제안한다. 제안 방법은 ZRP의 IERP에서 감청모드를 통하여 사용중인 경로보다 최적의 경로를 감지하여 새로운 경로로 갱신하는 방법과 중간 노드가 이동하여 경로가 깨진 경우 부분적으로 경로를 복구하는 방법을 제시하여 항상 최적화된 경로를 유지함으로써 Ad Hoc망의 위상변화에 대한 적응성을 높일 수 있도록 한다.기반으로 하는 교육용 애플리케이션 개발의 용이성의 증대를 기대할 수 있으며, 모델의 재사용성을 보장할 수 있다. 제안한다.수행하였다. 분석에서는 제품의 효율성뿐만 아니라 보안성을 중요하게 생각하였으며, 앞으로 보안 관련 소프트웨어 개발에 사용될 수 있는 도구들이 가이드 라인에 대한 정보를 제공한다.용할 수 있는지 세부 설계를 제시한다.다.으로서 hemicellulose구조가 polyuronic acid의 형태인 것으로 사료된다. 추출획분의 구성단당은 여러 곡물연구의 보고와 유사하게 glucose, arabinose, xylose 함량이 대체로 높게 나타났다. 점미가 수가용성분에서 goucose대비 용출함량이 고르게 나타나는 경향을 보였고 흑미는 알칼리가용분에서 glucose가 상당량(0.68%) 포함되고 있음을 보여주었고 arabinose(0.68%), xylose(0.05%)도 다른 종류에 비해서 다량 함유한 것으로 나타났다. 흑미는 총식이섬유 함량이 높고 pectic substances, hemicellulose, uronic acid 함량이 높아서 콜레스테롤 저하 등의 효과가 기대되며 고섬유식품으로서 조리 특성 연구가 필요한 것으로 사료된다.리하였다. 얻어진 소견(所見)은 다음과 같았다. 1. 모년령(母年齡), 임신회수(姙娠回數), 임신기간(姙娠其間), 출산시체중등(出産時體重等)의 제요인(諸要因)은 주산기사망(周産基死亡)에 대(對)하여 통계적(統計的)으로 유의(有意)한 영향을 미치고 있어 $25{\sim}29$세(歲)의 연령군에서, 2번째 임신과 2번째의 출산에서 그리고 만삭의 임신 기간에, 출산시체중(出産時體重

• Journal of KIISE
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• v.43 no.6
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• pp.710-717
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• 2016

Recently, several research studies on things abstraction framework have been proposed in order to implement the multi-service Internet of Things (IoT) system, where various IoT services share the thing devices. Distributed things abstraction has an IoT service duplication problem, which aggravates power consumption of mobile devices and network traffic. On the other hand, cloud server-centric things abstraction cannot cover real-time interactions due to long network delay. Fog server-centric things abstraction has limits in insufficient IoT interfaces. In this paper, we propose Smart Fog which is a fog server-centric things abstraction framework to resolve the problems of the existing things abstraction frameworks. Smart Fog consists of software modules to operate the Smart Gateway and three interfaces. Smart Fog is implemented based on IoTivity framework and OIC standard. We construct a smart home prototype on an embedded board Odroid-XU3 using Smart Fog. We evaluate the network performance and energy efficiency of Smart Fog. The experimental results indicate that the Smart Fog shows short network latency, which can perform real-time interaction. The results also show that the proposed framework has reduction in the network traffic of 74% and power consumption of 21% in mobile device, compared to distributed things abstraction.

• Journal of Advanced Navigation Technology
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• v.21 no.6
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• pp.554-560
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• 2017

Accurate altimetry is required for the reliable flight control of drones or unmanned air vehicles (UAVs), and the radar altimeter is commonly used owing to its accuracy for the ground level. Due to the limitation for size, weight and power consumption, the frequency modulated continuous wave (FMCW) radar is appropriate for drone because it has lower complexity than that of pulse Doppler (PD) radar. Especially, fast-ramp FMCW radar, which transmits linear FM signal during very short period, is generally utilized, because it is robust for the ego-motion of drone. Therefore, we present the design and implementation results of the radar signal processor (RSP) for fast-ramp FMCW radar system. The proposed RSP was designed with Verilog-HDL and implemented with Altera Cyclone-IV FPGA device. Implementation results show that the proposed RSP includes 27,523 logic elements, 15,798 registers and memory of 138Kbits and can measure the altimeter at the rate of 100Hz with the operating frequency of 50MHz.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.10 s.352
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• pp.1-9
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• 2006

In this paper, a couple of 10Gb/s transimpedance amplifiers are realized in a 0.18um standard CMOS technology for optical communication applications. First, the voltage-mode inverter TIA(I-TIA) exploits inverter input configuration to achieve larger effective gm, thus reducing the input impedance and increasing the bandwidth. I-TIA demonstrates $56dB{\Omega}$ transimpedance gain, 14GHz bandwidth for 0.25pF photodiode capacitance, and -16.5dBm optical sensitivity for 0.5A/W responsivity, 9dB extinction ration and $10^{-12}$ BER. However, both its inherent parasitic capacitance and the package parasitics deteriorate the bandwidth significantly, thus mandating very judicious circuit design. Meanwhile, the current-mode RGC TIA incorporates the regulated cascade input configuration, and thus isolates the large input parasitic capacitance from the bandwidth determination more effectively than the voltage-mode TIA. Also, the parasitic components give much less impact on its bandwidth. RGC TIA provides $60dB{\Omega}$ transimpedance gain, 10GHz bandwidth for 0.25pF photodiode capacitance, and -15.7dBm optical sensitivity for 0.5A/W responsivity, 9dB extinction ration and $10^{-12}$ BER. Main drawback is the power dissipation which is 4.5 times larger than the I-TIA.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.8
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• pp.16-21
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• 2007

CMOS variable gain amplifier (VGA) IC designs for the structure monitoring systems of the telemetries were developed. A three stage cascaded VGA using a differential amplifier and a linear-in-dB controller is presented. A proposed VGA is a modified version of a conventional VGA such that the gain is controlled in a linear-in-dB fashion through the current ratio. The proposed VGA circuit introduced in this paper has a dynamic range of 77 dB with 1.5 dB gain steps. It also achieved a gain error of less than 1.5 dB over 77 dB gain range. The VGA can operate up to 10MHz dissipating 13.8 mW from a single 1.8 V supply. The core area of the VGA fabricated in a Magnachip $0.18{\mu}m$ standard CMOS process was about $430{\mu}m{\times}350{\mu}m$. According to measurement results, we can verify that the proposed method is reasonable with regard to the enhancement of dynamic range and the better linear-in-dB characteristics.

• Clean Technology
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• v.23 no.1
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• pp.73-79
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• 2017

Recently usage of biomass is increased in pulverized coal power plants for reduction of $CO_2$ emission. Many problems arise when thermal share of the biomass is increased, and milling of the biomasses is one of the most important problems due to their low grindability when existing coal pulverizer is used. Grindability of coal can be measured through the HGI (Hardgrove grindability index) equipment as a standard, but method of measuring biomass grindability has not been established yet. In this study, grinding experiment of coal and biomass was performed using a lab-scale ball mill. One type of coal (Adaro coal) and six biomasses (wood pellet (WP), empty fruit bunch (EFB), palm kernel shell (PKS), walnut shell (WS), torrefied wood chip (TBC) and torrefied wood pellet (TWP)) were used in the experiment. Particle size distributions of the fuels were measured after being milled in various pulverization times. Pulverization characteristics were evaluated by portion of particles under the diameter of $75{\mu}m$. As a result, about 70% of the TBC and TWP were observed to be pulverized to sizes of under $75{\mu}m$, which implies that they can be used as alternative biomass fuels without modification of the existing mill. Other biomass was observed to have low grindability compared with torrefied biomass. Power consumption of the mill for various fuels was measured as well, and the results show that lower power was consumed for torrefied biomasses. This result can be used for characterization of biomass as an alternative fuel for pulverized coal power plants.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2000.05a
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• pp.465-469
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• 2000

This paper describes a single-chip full-custom implementation of pipelined adaptive decision-feedback equalizer (PADFE) using a 0.25-${\mu}{\textrm}{m}$ CMOS technology for wide-band wireless digital communication systems. To enhance the throughput rate of ADFE, two pipeline stage are inserted into the critical path of the ADFE by using delayed least-mean-square (DLMS) algorithm Redundant binary (RB) arithmetic is applied to all the data processing of the PADFE including filter taps and coefficient update blocks. When compared with conventional methods based on two's complement arithmetic, the proposed approach reduces arithmetic complexity, as well as results in a very simple complex-valued filter structure, thus suitable for VLSI implementation. The design parameters including pipeline stage, filter tap, coefficient and internal bit-width and equalization performance such as bit error rate (BER) and convergence speed are analyzed by algorithm-level simulation using COSSAP. The singl-chip PADFE contains about 205,000 transistors on an area of about 1.96$\times$1.35-$\textrm{mm}^2$. Simulation results show that it can safely operate with 200-MHz clock frequency at 2.5-V supply, and its estimated power dissipation is about 890-mW.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.4
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• pp.1-9
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• 2009

In this paper, a small area 12-bit 300MSPS CMOS Digital-to-Analog Converter(DAC) is proposed for display systems. The architecture of the DAC is based on a current steering 6+6 segmented type, which reduces non-linearity error and other secondary effects. In order to improve the linearity and glitch noise, an analog current cell using monitoring bias circuit is designed. For the purpose of reducing chip area and power dissipation, furthermore, a noble self-clocked switching logic is proposed. To verify the performance, it is fabricated with $0.13{\mu}m$ thick-gate 1-poly 6-metal N-well Samsung CMOS technology. The effective chip area is $0.26mm^2$ ($510{\mu}m{\times}510{\mu}m$) with 100mW power consumption. The measured INL (Integrated Non Linearity) and DNL (Differential Non Linearity) are within ${\pm}3LSB$ and ${\pm}1LSB$, respectively. The measured SFDR is about 70dB, when the input frequency is 15MHz at 300MHz clock frequency.

• Journal of the Institute of Electronics and Information Engineers
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• v.49 no.12
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• pp.56-63
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• 2012

The WBAN technology means a short distance wireless network which provides each device interactive communication by connecting devices inside and outside of body. Standardization on the physical layer, data link layer, network layer and application layer is in progress by IEEE 802.15.6 TG BAN. Wireless body area network is usually configured in energy efficient using sensor and zigbee device due to the power limitation and the characteristics of human body. Wireless sensor network consist of sensor field and sink node. Sensor field are composed a lot of sensor node and sink node collect sensing data. Wireless sensor network has capacity of the self constitution by protocol where placed in large area without fixed position. Mobile sink node distribute energy consumption therefore network life time was increased than fixed sink node. The energy efficient is important matter in wireless body area network because energy resource was limited on sensor node. In this paper we proposed cluster topology algorithm for efficient data transmission in wireless body area network based mobile sink. The proposed algorithm show good performance under the advantage of grid routing protocol and TDMA scheduling that minimized overlap area on cluster and reduced amount of data on cluster header in error prone wireless sensor network based on mobile sink.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.2
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• pp.118-124
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• 2008

For forward error correction, DVB-S2, which is the digital video broadcasting forward error coding and modulation standard for satellite television, uses a system based the concatenation of BCH with LDPC inner coding. In DVB-S2 the LDPC codes are defined for 11 different code rates, which means that a DVB-S2 LDPC decoder should support multiple code rates. Seven of the 11 code rates, 3/5, 2/3, 3/4, 4/5, 5/6, 8/9, and 9/10, are regular and the rest four code rates, 1/4, 1/3, 2/5, and 1/2, are irregular. In this paper we propose a flexible decoder for the regular LDPC codes. We combined the partially parallel decoding architecture that has the advantages in the chip size, the memory efficiency, and the processing rate with Benes network to implement a DVB-S2 LDPC decoder that can support multiple code rates with a block size of 64,800 and can configure the interconnection between the variable nodes and the check nodes according to the parity-check matrix. The proposed decoder runs correctly at the frequency of 200MHz enabling 193.2Mbps decoding throughput. The area of the proposed decoder is $16.261m^2$ and the power dissipation is 198mW at a power supply voltage of 1.5V.