• Proceedings of the KIPE Conference
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• 2005.07a
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• pp.140-142
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• 2005

SMPS의 손실에는 switching loss, conduction loss, core loss가 있다. 최근 SMPS에서는 switching loss를 줄여 효율을 높이고자 반도체 스위치 2개를 사용하는 공진형 구조가 증가하고 있다하지만 공진형 구조는 반도체 스위치에서 소비되는 conduction loss로 의해 기존의 컨버터에 비해 무부하시 전력 소모가 크다. 그러나 최근 시장은 무부하시 소비되는 대기전력의 규제가 이슈가 되고 있다. 본 논문에서는 active clamped flyback converter에서 무부하시 반도체 스위치의 conduction loss의 감소를 위해 Clamp 회로의 보조 스위치는 동작시키지 않고, flyback converter로만 동작하도록 설계하여 무부하시에는 기존의 flyback converter의 동작과 같이 도통 손실이 급속히 줄도록 하였다. 또한 스위칭 손실을 줄이기 위해 주 스위치의 동작 주파수를 감소시켜 SMPS의 무부하시의 소모를 감소시켰다. 70W급 SMPS의 제작과 실험을 통해 위의 방법을 증명하고자 한다.

• Proceedings of the KIPE Conference
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• 2005.07a
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• pp.128-130
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• 2005

본 논문은 ZVS asymmetrical half-bridge converter 에서 무부하시 전력소모 분석과 감소 방안에 대한 연구이다. Asymmetrical half-bridge converter는 영전압 스위칭을 통해 효율 증가가 가능하고, 낮은 EMI 발생의 장점으로 인해 최근 많이 사용되고 있다. 그러나 최근 이슈가 되고 있는 대기전력 소모의 관점에서는 기존의 hard switching converter에 비해 오히려 손실이 증가한다. 이는 공진형 컨버터의 무부하시 동작이 기생전류에 의한 도통손실이 크기 때문이다. 따라서 본 논문에서는 이를 개선 할 수 있는 방법을 제시하고 70W급의 실험용 SMPS의 제작을 통해 제안된 방법의 타당성을 검증한다.

• Journal of Software Engineering Society
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• v.24 no.2
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• pp.55-66
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• 2011

Component-based Software development(CBSD) is widely used in various area due to its efficiency of time, cost and effort. In the embedded software which has high dependency of platform and can be developed by product family, the efficiency of CBSD is maximized by reuse. These embedded software has various limitations of the resources. Specially, the effective energy consumption is very important in the portable embedded software such as smart phone and tablet PC, because they are operated with limited energy source like a battery. Therefore, energy efficient problem became very important issue in the CBSD. In this paper, we identified characteristics and environment that influence energy consumption of components. Afterward, we defined a component specification language which is consisted to describe energy characteristics of the components. This supposed specification language can be utilized to energy efficient component search and selection.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.39B no.12
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• pp.873-875
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• 2014

In this paper we describe an asynchronous MAC protocol with receiver-initiated duty cycling for energy-efficiency in wireless sensor networks(WSN). Legacy asynchronous MAC protocols, X-MAC and PW-MAC, has weaknesses which generates too many control packets and has data collision problem between multiple transmitters, respectively. Therefore, we propose a receiver-initiated asynchronous MAC protocol which generates control packets from transmitter to complement these disadvantages. Compared to the prior asynchronous duty cycling approaches of X-MAC and PW-MAC, the proposed protocol shows a improvement in energy-efficiency, throughput and latency from simulation results.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.34 no.2B
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• pp.151-161
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• 2009

The PULSE protocol can greatly reduce power consumption using a node's sleep state. But this protocol does not consider movement of a sink node in a sensor network. In the mobile sensor network a routing protocol must recover path error by movement of a sink node as quickly as possible. Therefore we have to achieve fast path recovery and power saving to support movement of a sink node in a sensor network. This paper proposes the Mobile PULSE protocol which is a improved routing protocol for a mobile sink node. And we evaluate Mobile PULSE and show that the Mobile PULSE reduces the recovery time about 40% compared with original PULSE protocol. Mobile PULSE increases energy consumption than PULSE as a maximum of 0.8%, which means Mobile PULSE is similar to PULSE in energy consumption. This paper shows mobile PULSE's capability in the mobile sensor network through evaluation of path recovery time and power consumption.

• Electrical & Electronic Materials
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• v.13 no.8
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• pp.15-26
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• 2000

플리주마 디스플레이는 시야각이 매우 넓으며 비선형성이 우수하고 수동 행렬 구동이 가능하다. 제조방법이 다른 표시 장치보다 간단하고 대형화가 용이하기 때문에 42인치 이상 대형 표시 장치로 많은 회사에서 플라즈마 디스플레이를 개발 및 상용화 하고 있다. 플라주마 디스플레이는 초기에는 PMD(Pulse Momory Drive) 및 NOA(Nomally On Anode) 방식으로 구동하는 DC PCP를 중심으로 개발되었으나, DC PDP의 소비 전력이 매우 크고 패널의 수명이 짧기때문에 더 이상 개발되지 않고 현재 AC PDP를 중심으로 개발 및 상용화가 되고있다. AC PDP를 구동하는 방법으로 어드레스 구간과 유지 방전구간이 완전히 분리된 ADS(Address Display Seperation) 방식과 유지방전이 진행하는 동나 어드레스를 하는 AWD(Address While Display) 방식이 있다. 그러나, ADS 나 AWD 방식으로 고해상도 고휘도의 PDP를 구동하기가 어렵기 때문에 고해상도의 PDP를 구동할 수 있는 ALiS, MAoD, MASS 방식 등이 개발되었다. 그리고, AC PDP는 유지 방전할 때, 패널에 고전압을 충전하고 방전하기 때문에 패널에서 소모하는 전력이 많아 이를 줄이기위해 에너지 회수 회로를 사용하여 전력 소모를 줄이고 있다. 본 논문에서는 PDP의 구조 및 동작원리에 대해서 설명하고, 계조를 표시하기 위한 구동 방법, 전력 소모를 감소기키기 위한 에너지 회수회로 및 구동회로에 대해서 기술하였다.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.38 no.2
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• pp.50-55
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• 2001

In this paper, a 8bit parity checker/generator is designed using a new gate which is proposed to implement the exclusive or(XOR) and exclusive-nor(XNOR) functions for low power consumption on transistor level. Conventional XOR/XNOR gate such as CPL, DPL and CCPL designed to reduce the power consumption has an inverter to get the full swing output signals. But this inverter consumes the major part of power and causes the time delay on CMOS circuits. Thus a new technique was adopted not utilizing inverter in the circuits. The results of simulation by Hspice shows 33% of power reduction compared with CCPL gate when A 8 bit parity checker was made with the proposed new gate using $0.8{\mu}mCMOS$ technology.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.25 no.8B
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• pp.1477-1486
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• 2000

This paper proposes an efficient kernel-based partitioning algorithm for reducing area and power dissipation in combinational circuit design.. The proposed algorithm decreases the power consumption by partitioning a given circuit utilizing a kernel, and reduces the area overhead by minimizing duplicated gates in the partitioned subcircuits. Experimental results for the MCNC benchmarks show that the proposed algorithm is effective by generating circuits consuming 43.6% less power with 30.7% less area on the average, when compared to the previous algorithm based on precomputation circuit structure.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.25 no.10A
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• pp.1582-1589
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• 2000

A dynamic D-flipflop is proposed aiming at low power and high frequency(GHz) operations. The proposed D-flipflop uses a smaller number of pmos transistors that it operates high speed in same dimensions. Also, it consumes lower power than conventional approaches by a shared nmos with clock input. In order to compare the performance of the proposed D-flipflop, we perform simulation estimating power consumption and maximum operating frequency of each same dimension D-flipflop. A high speed dual-modulus prescaler employing the proposed D-flipflop. A high speed dual-modulus prescaler employing the proposed D-flipflop. A high speed dual-modulus prescaler employing the proposed D-flipflop is evaluated via the same method. The simulation results show that the proposed D-fliplflop has good performance than conventional circuits.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.32 no.3A
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• pp.221-229
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• 2007

In this paper, we propose and analyze the optimized sleep mode for a mobile node (MN) in IEEE 802.16e wireless metropolitan area networks. Because a MN in a sleep mode specified in 802.16e specification should maintain state information with the base station currently attached, it must renew sleep state with a new base station after handover which leads to unnecessary waste of battery power. Noting that the mobility pattern of a MN is independent of call arrival patterns, we propose an optimized sleep mode to eliminate unnecessary standby period of a MN in sleep state after handover. We also propose an analytical model for the proposed scheme in terms of power consumption and the initial call response time. Simulation studies that compare the performance between the sleep mode and the optimized sleep mode show that our scheme marginally increases initial call response delay with the huge reduction in power consumption.