• Proceedings of the KIEE Conference
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• 2005.07c
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• pp.2262-2264
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• 2005

지금까지 변전소나 개폐소에서 전류, 전압을 계측하는 수단으로서 주로 철심과 권선으로 구성되어진 변류기(CT), 계기용 변압기(PT, PD)가 사용되어져 왔다. 최근, 2차측의 계측기나 보호 Relay의 Digital화가 진전되어 또한 이것을 Digital Network으로 총합한 Intelligent 변전소의 구축이 검토되어지고 있으며, Digital Network에 대응한 변성기 관련규격인 IEC 60044가 근래 제정되어짐에 따라 이에 적합한 전자식 변성기가 요구되어지고 있다. 상기와 같은 요구로 인해 당사에서는 IEC 60044를 기반으로 한 전자식변성기 Layout을 구성하였으며, CT는 검출부에 Rogowski Coil을 적용하며 그 후단에 적분기를 설치하였으며, VD는 검출부에 중간 전극을 이용해서 분압하는 방식인 Capacitive Voltage Divider를 사용하고 증폭기를 삽입하여, 각각 요구되는 전압 신호를 얻었다. 이러한 신형 CT/VD의 적용으로 종래의 CT/PT가 차지하는 공간이 필요없게 되어 컴팩트한 GIS의 구조가 가능하게 되어 있다.

• Journal of the Korean Society of Surveying, Geodesy, Photogrammetry and Cartography
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• v.27 no.4
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• pp.437-444
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• 2009

A bi-directional, multi-step numerical integrator is developed to determine the GPS (Global Positioning System) orbit based on a dynamic approach, which shows micrometer-level accuracy at GPS altitude. The acceleration due to the planets other than the Moon and the Sun is so small that it is replaced by the empirical forces in the Solar Radiation Pressure (SRP) model. The satellite orbit parameters are estimated with the least-squares adjustment method using both the integrated orbit and the published IGS (International GNSS Service) precise orbit. For this estimation procedure, the integration should be applied to the partial derivatives of the acceleration with respect to the unknown parameters as well as the acceleration itself. The accuracy of the satellite orbit is evaluated by the RMS (Root Mean Squares error) of the residuals calculated from the estimated orbit parameters. The overall RMS of orbit error during March 2009 was 5.2 mm, and there are no specific patterns in the absolute orbit error depending on the satellite types and the directions of coordinate frame. The SRP model used in this study includes only the direct and once-per-revolution terms. Therefore there is errant behavior regarding twice-per-revolution, which needs further investigation.

• Transactions of the Korean Society of Mechanical Engineers
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• v.15 no.5
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• pp.1763-1773
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• 1991

본 연구에서는 포화수증기와 공기의 혼합기내에서 분무수적으로의 열 및 질량 전달률을 계산하기 위하여 수적의 부분혼합모형과 비혼합모형에 대하여 수적내 과도온 도분포의 해석해를 적용성이 보장되면서도 계산상의 어려움이 수반되지 않는 형태로 구하기 위하여 수적내부의 열전도해석에 있어서 적분법을 적용하였다. 적분법으로 얻어지는 과도온도분포의 해는 유한차의 다항식으로 표시되어 비혼합모형인 경우 각시 간 구간의 경계에서의 온도분포가 연속성을 유지하면서 물성치들의 온도에 대한 종속 성이 쉽게 고려되고 계산도 용이한 형태이다. 본 보에서 제시하는 해석결과의 적용 성을 조사하기 위하여 완전혼합모형을 포함하는 세가지 수적모형들에 대한 계산결과들 로부터 얻어진 시간변화에 따른 수적의 무차원 체적평균온도변동을 유효한 실험결과들 과 비교, 검토하였으며, 부분혼합모형에 대하여 혼합기의 압력, 수적의 초기온도, 혼 합기 속에 포함되어 있는 수증기의 체적분율, 수적의 초기크기, 수적의 초기속도 및 분사각도가 주위혼합기로부터 수적으로 전달되는 열 및 질량전달에 미치는 영향을 조] 사하고 도출된 대표적인 검토 결과를 제시하였다.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.40 no.4
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• pp.34-41
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• 2003

A new technique for detecting parametric faults in mixed signal circuits is proposed Pseudo-random sequence from linear feedback shift register(LFSR) is fed to circuit-under-test (CUT) as stimulus and wavelets are used to compact the transient response under this stimulus into a small number of signature. Wavelet based scheme decomposes the transient response into a number of signal in different frequency bands. Each decomposed signal is compacted into a signature using digital integrator. The digital pulses from LFSR, owing to its pseudo-randomness property, are almost uniform in frequency domain, which generates multi-frequency response when passed through CUT. The effectiveness of this technique is demonstrated in our experimental results.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.44 no.4 s.316
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• pp.61-66
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• 2007

PID control is windely used to control stable processes, however, its application to integrating processes is less common. In this paper we proposed a simple PID controller tuning method for integrating processes with time delay to meet a stable specification. With the proposed PID tuning method, we can obtain stable integrating processes using PD controller in inner feedback loop and a loop transfer function with desired stable specification. This guarantees bout robustness and performance. Simulation examples are given to show the good performance of the proposed tuning method to other methods.

• The Transactions of the Korean Institute of Power Electronics
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• v.11 no.5
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• pp.395-403
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• 2006

This paper has proposed a new dead time compensation method for a voltage-fed PMW inverter. In the voltage-fed PMW inverter, a voltage distortion is generated by the dead time effect and the nonlinear characteristics of the switching devices. Especially, the distorted voltage causes 5th and 7th harmonics in the stationary phase currents, and 6th harmonic in the synchronous phase currents. As a result, the integrator output of the synchronous PI current regulator has the ripple corresponding to six times of the inverter output frequency. In this paper, the signal of the integrator output of the d-axis current regulator is used as the control signal for the dead time compensation. The experimental and simulation results are presented to verify the validity of the proposed method.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.28 no.4A
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• pp.200-207
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• 2003

This paper proposes a CDMA receiver structure with time-shifted m-sequence orthogonal reception process, and analyzes the output SNR performance and the characteristics of the orthogonal receiver. This structure can be simply implemented with the converntional receiver adding an additional integrator path in parallel and an adder sums the conventional path and the new path output signals. The structure provides to reference user signal not only increment of signal component but also perfect orthogonal characteristic, canceling the accumulated cross-correlated value out to zero between the reference user and other user signals. Hence, the proposed structure can be applied for channel impulse response measurement, and used for multi-user interference signal cancellation and channel capacity increment by flexible structural inter-working operation of the added path, connection or disconnection, to conventional receiver structure.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.2
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• pp.121-126
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• 2007

This paper describes a 9.09 Gb/s CMOS demultiplexer using redundant multi-valued logic (RMVL). The proposed circuit receives serial binary data and is converted to parallel redundant multi-valued data using RMVL. The converted data are reconverted to parallel binary data. By the redundant multi-valued data conversion, the RMVL makes it possible to achieve higher operating speeds than that of a conventional binary logic. The implemented demultiplexer consists of eight integrators. Each integrator is composed of an accumulator, a window comparator, a decoder and a D flip flop. The demultiplexer is designed with Samsung $0.35{\mu}m$ standard CMOS process. The validity and effectiveness are verified through the post layout simulation. The demultiplexer is achieved the maximum data rate of 9.09 Gb/s and the average power consumption of 69.93 mW. This circuit is expected to operate at higher speed than 9.09 Gb/s in the deep-submicron process of the high operating frequency.

• Journal of IKEEE
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• v.19 no.1
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• pp.87-93
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• 2015

In this paper, a $145{\mu}W$, 87dB SNR, Low power 3rd order Sigma-Delta Modulator with Op-amp sharing is proposed. Conventional architecture with analog path and digital path is improved by adding a delayed feed -forward path for disadvantages that coefficient value of the first integrator is small. Proposed architecture has a larger coefficient value of the first integrator to remove the digital path. Power consumption of proposed architecture using op-amp sharing is lower than conventional architecture. Simulation results for the proposed SDM designed in $0.18{\mu}m$ CMOS technology with power supply voltage 1.8V, signal bandwidth 20KHz and sampling frequency 2.8224MHz shows SNR(Signal to Noise Ratio) of 87dB, the power consumption of $145{\mu}W$.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.48 no.12
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• pp.37-44
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• 2011

This paper presents the method of improving the data rate and BER in the inductive coupling link using a BPM signaling method. A complementary switching transmitter is used to remove invalid glitches at transmitted data, and the concept of pre-distortion is introduced to optimize received data. Also, an integrating receiver is used to increase the sampling margin and equalizing transistors are added in the pre-charge path of the integrator and comparator for high frequency operation. The transceiver designed with a 0.13 um CMOS technology operates at 2.4 Gb/s and consumes 5.99 mW from 1.2 V power supply.