• The KIPS Transactions:PartA
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• v.15A no.2
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• pp.69-74
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• 2008

This paper proposes a structure of low-power MOS current-mode logic circuit with sleep-transistor to reduce the leakage current. The sleep-transistor is used to high-threshold voltage transistor to minimize the leakage current. The $16\;{\times}\;16$ bit parallel multiplier is designed by the proposed circuit structure. Comparing with the conventional MOS current-model logic circuit, the circuit achieves the reduction of the power consumption in sleep mode by 1/50. This circuit is designed with Samsung $0.35\;{\mu}m$ CMOS process. The validity and effectiveness are verified through the HSPICE simulation.

• Journal of the Institute of Electronics and Information Engineers
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• v.51 no.4
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• pp.59-65
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• 2014

In this paper, in order to improve efficiency performance of power amplifiers, a mode changeable autotransformer is proposed. Efficiency performance at the low-power mode can be improved by adopting the mode changeable autotransformer. A dual-mode autotransfomrer CMOS power amplifier using a standard 0.18-${\mu}m$ CMOS process is designed in this work. Number of turns in a primary winding is re-configurated according to mode change between the high-power mode and the low-power mode. Thus, the efficiency performance of the power amplifier at each mode is optimized. EM and total circuit simulation results verify that low-power mode power added efficiency(PAE) at 24dBm output power is improved from 10.4% to 26.1% using the proposed multi-mode operation.

• Proceedings of the IEEK Conference
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• 2001.09a
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• pp.701-704
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• 2001

본 논문은 영상압축 표준의 하나로 표준화가 진행중 인 H.26L에 효율적인 저전력 움직임 추정 구조를 제안한다. 제안하는 방식은 움직임 추정에 사용하는 이전 프레임에서의 움직임 벡터 발생 빈도와 경향을 이용하여 계산량과 수행시간을 줄인다. 그리고 가변 블럭 정합을 고려하여 먼저 최소 블럭 크기 단위로 블럭 SAD를 계산한 후 다른 모드 블럭 SAD 를 계산으로 생성한다. 제안하는 방식은 기존의 저전력 블럭 정합 방식과 비교하여 최대 31% 전력 소모 감소가 이루어지며 완전 전역 탐색 블럭 정합 방식에 비해 평균 75-90%의 계산량이 감소된다.

• Proceedings of the IEEK Conference
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• 2007.07a
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• pp.75-76
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• 2007

이 논문에서는 IS-95와 WCDMA의 Multi-mode로 동작하는 Multi-mode용 저전력 DDC filter 구조를 제안한다. 기존의 DDC구조의 경우 CIC의 통과대역 특성을 향상시켜 주지만, 저지대역의 감쇠특성은 오히려 나빠지는 문제점을 안고 있었다. 제안된 구조는 CIC 데시메이션 필터의 통과대역 특성은 더욱 향상시켜주며, 저지대역의 감쇠특성도 같이 향상시키는 특징을 가진다. 또한 제안된 절터는 각 필터의 면적을 감소시키기 위해 IS-95와 WCDMA의 각각의 모드에 대해 한 개의 필터를 설계한 후 각 모드에 따라 필터 탭 수를 달리하여 동작하는 Multi-mode의 저전력 구조로 구현하였다.

• Proceedings of the Korean Information Science Society Conference
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• 2010.06d
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• pp.432-435
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• 2010

네트워크 기기분야에서는 정보통신기기 및 고속 멀티미디어 데이터 수요의 증가에 따라 네트워크 기기의 전력소비가 꾸준히 증가하고 있다. 특히 홈 네트워크 기기들은 전원이 연결되어 있는 상태로 동작하여 데이터 통신이 발생하지 않는 상황에서도 일정한 전력소모가 발생하므로 이에 대한 대처기술이 마련되어야 한다. 본 논문에서 대기전력 지원 홈게이트웨이 시스템 구현을 위하여 하드웨어를 설계하고 저전력 대기모드 지원 네트워크 프로토콜 인터페이스 개발하였으며 홈게이트웨이 시뮬레이터 S/W를 개발하여 홈게이트웨이의 기능을 시험테스트 하였다. 시뮬레이터 시험결과 각 네트워크 포트에서 발생된 트래픽에 따라 홈게이트웨이의 전원 모드가 변경됨을 확인할 수 있었으며 대기모드 시 소모 전력이 1W 미안으로 측정되었다.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.11 s.353
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• pp.98-104
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• 2006

The conventional burst-mode APC(Automatic Power Control) circuit had an effective structure that was suitable for a low power consumption and a monolithic chip. However, as data rate was increased, it caused errors due to the effect of the zero density. In this paper, we invented a new structured peak-comparator which could compensate the unbalance of the injected currents using double gated MOS and MOS diode. And we proposed a new burst-mode APC adopting it. The new peak-comparator in the proposed APC was very robust to zero density variations maintaining the correct decision point of the current comparison at high data rate. It was also suitable for a low power consumption and a monolithic chip due to lack of large capacitors.

• The Journal of the Korea institute of electronic communication sciences
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• v.14 no.6
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• pp.1145-1152
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• 2019

In this paper, a low power current mode 12-bit ADC(: Analog to Digital Converter) is proposed to mix digital circuits and analog circuits with the advantages of low power consumption and high speed operation. The proposed 12 bit ADC is implemented by using 4-bit ADC in a cascade structure, so its power consumption can be reduced, and the chip area can be reduced by using a conversion current mirror circuit. The proposed 12-bit ADC is SK Hynix 350nm process, and post-layout simulation is performed using Cadence MMSIM. It operates at a supply voltage of 3.3V and the area of the proposed circuit is 318㎛ x 514㎛. In addition, the ADC shows the possibility of operating with low power consumption of 3.4mW average power consumption in this paper.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.18 no.8
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• pp.1877-1884
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• 2014

Because of the limited power resource, we need a reliable low-power media access control technique suitable for unmaned remote sensor operation condition for the unmanned sensor processor to perform the task in the remote wireless network situation. Therefore CSMA/CA and X-MAC is generally considered to effectively transmit the signal in the low-power wireless network. In this paper, we propose the more efficient low-power LP-MAC Technique which consumes the minimum power and transmits the data faster in condition that the mobile nodes' joining to and leaving from the network which consists of the fixed nodes is fluid. The fixed nodes operate in an asynchronous mode to perform the network self-configuration and transmit data faster to the mobile node which is frequently join and leave the network. When the mobile node leaves the network, the network's operation mode will be synchronous mode to achieve the minimum power consumption, thus the minimum power operation becomes possible.

• Journal of Korea Game Society
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• v.6 no.4
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• pp.63-70
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• 2006

This paper studied various low power structures of texture caches for mobile 3D graphics accelerator to reduce the memory latency of texture data. Also the paper designed the texture cache with the variable threshold values of power mode transition according to the filtering algorithms. In the trace driven simulation, we compared the performance of those structures using Quake game engine as the benchmark. Also the algorithm was proposed and verified by the simulation, which has variable threshold values of power mode transitions according to the selected texture filtering method.

• Journal of Korea Society of Industrial Information Systems
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• v.18 no.5
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• pp.25-32
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• 2013

A 1.8V 2-Gb/s scalable low voltage signaling (SLVS) transmitter (TX) is designed for mobile applications requiring high speed and low power consumption. It consists of 4-lane TX for data transmission, 1-lane TX for a source synchronous clocking, and a 8-phase clock generator. The proposed SLVS TX has the scaling voltage swing from 50 mV to 650 mV and supports a high speed (HS) mode and a low power (LP) mode. An output impedance calibration scheme for the SVLS TX is proposed to improve the signal integrity. The proposed SLVS TX is implemented by using a 0.18-${\mu}m$ 1-poly 6-metal CMOS with a 1.8 V supply. The simulated data jitter of the implemented SLVS TX is about 8.04 ps at the data rate of 2-Gb/s. The area and power consumption of the 1-lane of the proposed SLVS TX are $422{\times}474{\mu}m^2$ and 5.35 mW/Gb/s, respectively.