• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.8
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• pp.93-98
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• 2004

A low power SRAM using elevated source level memory cells is proposed to save the write power of SRAM. It reduces the swing voltages of the bit lines and data bus by elevating the source level of the memory cells from GND to $V_{T}$ and lowering the precharge level of the bit lines and data bus from $V_{DD}$ to $V_{DD}$ - $V_{T}$. It saves the write power of SRAM without area overhead and speed degradation. An SRAM with 8K${\times}$32bits is fabricated in a 0.25um CMOS process. It saves 45% of the power in write cycles at 300MHz with 2.5V. The maximum operating frequency is 330MHz.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.29 no.10C
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• pp.1451-1459
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• 2004

In this paper, a low-power 32-point IMDCT structure is proposed for MP3. Through re-odering of IMDCT matrices, we propose the systolic structure operating with 16, 8, 4, 2, and 1 cycle, respectively. To reduce power consumption, multiplication of each sub blocks are implemented by add and shift operation with CSD(Canrmic sigled digit) form coefficients. To reduce, furthermore, the number of adders, we utilize the common sub-expression sharing techniques. With these techniques, the relative power consumption of the proposed structure is reduced by 58.4% comparison to the conventional structure using only 2's complement form coefficient. Validity of the proposed structure is proved through Verilog-HDL coding.

• Journal of Satellite, Information and Communications
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• v.8 no.3
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• pp.10-14
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• 2013

In this paper, when applying current-mode circuit design technique showing constant power dissipation none the less operation frequency, to the low power design of dynamic voltage frequency scaling, we introduce the low power current-mode circuit design technique applying MOSFET in sub-threshold region, in order to solve the problem that has large power dissipation especially on the condition of low operating frequency. BSIM 3, was used as a MOSFET model in circuit simulation. From the simulation result, the power dissipation of the current memory circuit with sub-threshold MOSFET showed $18.98{\mu}W$, which means the consumption reduction effect of 98%, compared with $900{\mu}W$ in that with strong inversion. It is confirmed that the proposed circuit design technique will be available in DVFS using a current-mode circuit design.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.18 no.8
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• pp.1877-1884
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• 2014

Because of the limited power resource, we need a reliable low-power media access control technique suitable for unmaned remote sensor operation condition for the unmanned sensor processor to perform the task in the remote wireless network situation. Therefore CSMA/CA and X-MAC is generally considered to effectively transmit the signal in the low-power wireless network. In this paper, we propose the more efficient low-power LP-MAC Technique which consumes the minimum power and transmits the data faster in condition that the mobile nodes' joining to and leaving from the network which consists of the fixed nodes is fluid. The fixed nodes operate in an asynchronous mode to perform the network self-configuration and transmit data faster to the mobile node which is frequently join and leave the network. When the mobile node leaves the network, the network's operation mode will be synchronous mode to achieve the minimum power consumption, thus the minimum power operation becomes possible.

• Proceedings of the Korean Information Science Society Conference
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• 2004.04a
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• pp.109-111
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• 2004

본 논문에서는 LCD 디바이스의 프레임버퍼 모니터링에 기반한 소프트웨어 단계의 저전력 LCD 관리 기법을 제시한다. 제안하는 기법은 Refresh-rate를 조절하여 기존 하드웨어에서 추가설비 없이 사용 가능하며, 커널 레벨로 동작하여 어플리케이션의 수정이 필요 없으며, 프레임 버퍼 모니터링을 통해 디스플레이의 퀼리티 보장이 가능한 특징을 가진다. 본 시스템은 Linux 운영체제 하에서 실제 구현되고, 실험을 통해 제안하는 기법이 사용자의 디스플레이 퀼리티 요구를 만족시키면서 저전력 관리를 수행할 수 있음을 밝힌다.

• Proceedings of the Korea Information Processing Society Conference
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• 2006.05a
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• pp.1371-1374
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• 2006

센서 네트워크는 관찰 지역 내의 정보를 수집하는 센서 노드들로 구성된다. 센서 노드는 제한된 용량의 배터리를 갖고 동작하므로 센서 노드의 배터리 파워를 효과적으로 사용하여 최대한 센서 노드의 수명을 길게 하는 것이 센서 네트워크의 중요한 고려사항 중의 하나이다. 센서 네트워크에서 사용되는 운영체제들은 이를 위해 대부분 저전력 모드를 고려하여 설계된다. 무선 임베디드 센서 네트워크를 위해 설계된 운영체제인 TinyOS도 간단하며 강력한 전력관리 기법을 제공한다. 그러나 TinyOS에서 제공하는 전력관리 기법은 마이크로컨트롤러 자체의 저전력 모드를 고려하지 않아서 마이크로컨트롤러가 제공하는 저전력 모드를 실제로 충분히 사용할 수 없다. 본 논문에서는 TinyOS에서 마이크로컨트롤러의 저전력 모드를 충분히 활용할 수 있도록 개선하여 보다 향상된 전력관리 기법을 제안한다.

• Journal of the Korean Institute of Intelligent Systems
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• v.19 no.1
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• pp.145-151
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• 2009

Orthogonal Frequency Division Multiplexing (OFDM) has been focused on as 4th generation communication method for realization of Ubiquitous Network in land mobile communications services, and has been a standard technology of Wireless Local Area Network (WLAN) for a High Date Rate communication. And in maritime data communication using high frequency (HF) band, 32-point FFT OFDM system is recommended by International Telecommunication Union (ITU). Maritime communication should be kept on connecting when maritime accident or the maritime disaster happen. Therefore, main device FFT should be operated with low power consumption. In this paper we propose a low power 32-point FFT algorithm using radix-2 and radix-4 for low power operation. The proposed algorithm was designed using VHSIC hardware description language (VHDL), and it was confirmed that the output value of Spartan-3 field-programmable gate array (FPGA) board corresponded to the output value calculated using Matlab. The proposed 32-point FFT algorithm will be useful as a leading technology in a HF maritime data communication.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.40 no.10
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• pp.2006-2013
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• 2015

In this paper we propose a multi-protocol gateway system based on low power wireless communications. The proposed multi-protocol gateway system was designed to allow real-time monitoring and control of the on-site situation through wired and wireless networks by gathering information for streetlight power control and environmental monitoring. The sensing data using multi-sensors with composite processing that selectively used wired or wireless communication (e.g., CDMA, Ethernet (TCP/IP), GPS, etc.) were designed to act as intermediaries that transmitted to the main server through ZigBee. Inaddition, they were designed by separating a CPU board and baseboard to ensure low maintenance cost and ease of hardware replacement. The proposed multi-protocol gateway system's power, impact, continuous operation stability, and immunity test results obtained a normal operation success rate of over 95% and normal continuous operation results. Moreover, in the voltage drop test, instantaneous immunity test, and conductive RF electromagnetic field immunity test, it obtained an average rating result of "A".

• Proceedings of the Korean Society of Computer Information Conference
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• 2013.01a
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• pp.13-16
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• 2013

최근 Web 서비스, MP3, 동영상 재생, 무선통신 등 다양한 기능을 제공하는 스마트폰, 테블릿 PC와 같이 베터리로 동작하는 디지털 컨버젼스 기기들의 사용량이 증가되었고, 이러한 이동형 임베디드 기기들은 베터리 용량에 따라 사용시간이 제한된다. 그렇기 때문에 기기들의 평가항목 중 전력소모라는 성능지표가 대두되고 있으며, 소비전력을 낮추기 위한 저전력 기법이 전 세계적으로 연구되고 있다. 본 논문에서는 이동형 임베디드 기기에 사용 가능한 cnu_RTOS에 DPM(Dynamic Power Management)과 S3C2450에서 제공하는 DPM(Device Power Management)을 이용한 저전력 기능을 구현하여, 소비전력 감소율을 측정하였다.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.36C no.4
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• pp.17-29
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• 1999

This paper presents a high level synthesis method targeting low power consumption for data-dominated CMOS circuits (e.g., DSP). The high level synthesis is divided into three basic tasks: scheduling, resource and register allocation. For lower power scheduling, we increase the possibility of reusing an input operand of functional units. For a scheduled data flow graph, a compatibility graph for register and resource allocation is formed, and then a special weighted network is then constructed from the compatibility graph and the minimum cost flow algorithm is performed on the network to obtain the minimum power consumption data path assignment. The formulated problem is then solved optimally in polynomial time. This method reduces both the switching activity and the capacitance in synthesized data path. Experimental results show 15% power reduction in benchmark circuits.