• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.8 no.5
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• pp.149-157
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• 2008

In this paper, a POI(Point-of-Interest) telematics service platform, in which detailed POI telematics services are discovered automatically and provided, is developed. The platform discovers services with UPnP middleware and provides a location-based service using GIS information. It is implemented by a telematics server, terminals, and service gateways and tested by applying test scenario for validation. Also, the response time and throughput of UPnP messages in the platform is measured and analyzed. The result shows that it has little impact on the service network congestion.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.18 no.9
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• pp.2189-2196
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• 2014

In this paper, a VLIW(Very Long Instruction Word) vision coprocessor which can efficiently accelerate computer vision algorithm for automotive is designed. The VLIW coprocessor executes four instructions per clock cycle via 8-stage pipelined structure and has 36 integer and floating-point instructions to accelerate computer vision algorithm for pedestrian detection. The processor has about 300-MHz operating frequency and about 210,900 gates under 45nm CMOS technology and its estimated performance is 1.2 GOPS(Giga Operations Per Second). The vision system composed of vision primitive engine and eight VLIW coprocessors can execute pedestrian detection at 25~29 frames per second(FPS). Because the VLIW coprocessor has high detection rate and loosely coupled interface with host processor, it can be efficiently applicable to a wide range of vision applications.

• The Journal of The Korea Institute of Intelligent Transport Systems
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• v.12 no.1
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• pp.109-120
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• 2013

In this paper we proposed the design of the hybrid road lighting control system using solar-light generation. The proposed hybrid road lighting control system be power offer through hybrid controller using Solar-Light Generation, and it is designed so that it can control lighting up. To control supply of continuous power when during power shortages. And the gateway be transmit control command using zigbee to road lighting to ensure that automatic lighting control on human sensing. In this case, the gateway is apply the lighting control algorithm that decisions to the status of the system by a pre-set time schedule and be able to operate. In this paper, the proposed efficiency analysis results of a hybrid road lighting control system was consumed power of 129.6W per day, 3.8KW per month, 47.3KW per annual. As a result, it were able to increase the energy efficiency than existing lighting control system by reduce power consumption of 76.2% and the electricity prices of 76.8%.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.37C no.11
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• pp.1162-1169
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• 2012

One of the important operational requirements for mission critical Ethernet networked system is having the fault tolerant capability. Such capability can be obtained by equipping multiport Network Interface Card (NIC) in each node in the system. Conventional NIC uses two or more Media Access Controls (MACs) and a co-processor for the MAC switching whenever an active port fails. Since firmware is needed for the co-processor, longer fail-over switching and degraded throughput can be generally expected. Furthermore the system upgrading requiring the firmware revision in each tactical node demands high cost. In this paper we propose a novel single MAC based NIC that does not use a co-processor, but just use general discrete building blocks such as MAC chip and switching chip, which results in better performances than conventional method. Experimental results validate our scheme.

• Journal of Advanced Navigation Technology
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• v.19 no.6
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• pp.581-586
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• 2015

In this paper, we configure a Radio Frequency IDentification (RFID) gateway using an arduino and raspberry pi which are recent issues with a representative open source hardware. RFID technology is emerging as a key technology in a variety of environments as a technique to automatically identify objects using a radio frequency signal. In this paper, we propose a distributed RFID gateway for providing various communication methods and processing a large amount of RFID tag information efficiently, and to increase the scalability and middleware communication efficiency of the RFID reader. Existing RFID middleware systems have the problems that they should adhere the web service for interworking with a reader and the communication standard. Therefore, in this paper, we comprise our RFID gate to satisfy not only the serial communication configuration but also various digital signal processing standard so that it increases the communication efficiency of the middleware system.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.1
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• pp.107-116
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• 2009

Quantum-dot Cellular Automata (QCA) is one of the most promising next generation nanoelectronic devices which will inherit the throne of CMOS which is the domineering implementation technology for large scale low power digital systems. In late 1990s, the basic operations of the QCA cell were already demonstrated on a hardware implementation. Also, design tools and simulators were developed. Nevertheless, its design technology is not quite ready for ultra large scale designs. This paper proposes a new approach which enables the QCA designs to inherit the verification methodologies and tools of CMOS designs, as well. First, a set of disciplinary rules strictly restrict the cell arrangement not to deviate from the predefined structures but to guarantee the deterministic digital behaviors is proposed. After the gate and interconnect structures of. the QCA design are identified, the signal integrity requirements including the input path balancing of majority gates, and the prevention of the noise amplification are checked. And then the digital logic is extracted and stored in the OpenAccess common engineering database which provides a connection to a large pool of CMOS design verification tools. Towards validating the proposed approach, we designed a 2-bit adder, a bit-serial adder, and an ALU bit-slice. For each design, the digital logic is extracted, translated into the Verilog net list, and then simulated using a commercial software.

• Journal of the Institute of Electronics and Information Engineers
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• v.52 no.10
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• pp.56-63
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• 2015

Not only performance analysis but also power analysis at early design stages is important in designing a system-on-chip. We propose a power modeling based on clock gating enable signals that enables accurate power analysis at a high-level. Power state is defined as combinations of the values of the clock gating enable signals and we can extract the clock gating enable signals to generate the power model automatically. Experimental results show that the average power accuracy is about 96% and the speed gain of power analysis at the high-level power is about 280 times compared to that at the gate-level.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.27 no.1A
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• pp.66-72
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• 2002

In this paper, we implemented the GenJTAG, a CAD tool, which generates a code of boundary scan circuit supporing a board level testing and d BIST(Built-In Self Test) written in verilog-HDL. A boundary scan circuit code that supports user's own BIST instructions is generated based on the informations from the users. Most CAD tools hardly allow users to add their own BIST instructions because the generated code described in gate-level. But the GenJTAG generates a behavioral boundary scan circuit code so users can easily make a change on the generated code.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.26 no.11B
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• pp.1595-1599
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• 2001

In this paper, we have desired and implemented of ASK modulator MMIC operating at 5.8 GHz for OBE used in AGPS(Automatic Gate Passing System). The proposed ASK modulator MMIC was implemented to apply a single supply voltage of 3 V to the drain in order to decrease ACP(Adjacent Channel Power). As a result, it is exhibits a broad linear modulation range from 0.7 V to 3 V and an On/off characteristic over 40 dB. The layouts of ASK modulator MMICs was designed and fabricated by using ETRI 0.57m MESFET library The chip size was 1.0mm $\times$x1.0mm.

• Proceedings of the KIPE Conference
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• 2019.07a
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• pp.68-70
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• 2019

본 논문은 8.1kW/L($132W/in^3$)의 전력밀도를 갖는 전기자동차(xEV)용 저전압 배터리 충전기(Low voltage DC-DC converter, LDC)를 위한 절연형 DC-DC컨버터의 설계 방법을 제안한다. 전체 부피 중 가장 큰 비중을 차지하는 자성체의 부피를 줄이기 위해 GaN소자를 채택하여 700kHz의 스위칭 주파수를 적용하였으며, GaN 스위치를 고주파에서 원활히 동작시키기 위한 게이트 드라이버를 직접 제작하였다. 또한 자속 상쇄 개념이 적용된 매트릭스 평면 변압기를 설계하여 적용함으로써 변압기의 부피를 크게 줄일 수 있었고, 8.1kW/L의 전력밀도를 달성하였다. 본 논문에서는 후보 토폴로지들의 비교를 통해 고 전력 밀도에 가장 적합한 토폴로지를 선정하였으며, 자속 상쇄 기법이 적용된 매트릭스 평면 변압기의 설계방법을 제안하였다.