• Proceedings of the Korea Society for Simulation Conference
• /
• 1998.10a
• /
• pp.7-11
• /
• 1998

ATM 망을 효율적으로 구축하고 여러 가지 형태의 제어를 통하여 망 자원을 안정적으로 관리하기 위해서는 망의 성능에 대한 다양한 관점에서의 분석이 필수적이며, 그 기본이 되는 것이 ATM 다중화기에 대한 성능 분석이다. ATM 다중화기에 입력되는 트래픽을 분석하는데 있어서 MRP(Markov Renewal Processes) 또는 SMP(Semi-Markov Processes)는 자동 상관계수를 계산하기가 비교적 용이해서 높은 양의 상관관계를 가지는 버스티한 트래픽을 표현하기에 적절한 구조를 가지고 있으며, 입력 트래픽의 머무는 시간이 어떠한 분포이든 표현 가능한 장점이 있다. 본 연구에서는 ATM 트래픽을 분석하는데 있어서 입력되는 on/off 소스를 MRP로 모형화하고, 이를 도착과정으로 하는 이산시간 MR/D/1B 대기시스템으로 구성하여 ATM 다중화기의 셀 손실확률 등의 성능분석을 제시한다. 또한 본 연구에서 제시한 방법에 대한 타당성 검증을 위하여 시뮬레이션과 비교 검토한다.

• Proceedings of the Korean Society of Broadcast Engineers Conference
• /
• 1999.11b
• /
• pp.85-89
• /
• 1999

재다중화기는 여러 개의 TS를 입력으로 받은 후 다중화하여 출력하는 시스템이다. 이를 위해서는 PSI 재구성 및 PID 재배열 등의 과정을 거친 후 T-STD 모델에 맞게 다중화하고, PCR 수정하여 전송하는 기능이 필요하다. 재다중화기는 부가적으로 MPEG 스트림을 끊어 잇는 스플라이싱 기능과 PSI와 PSIP의 상호 연계를 위해 PSIP 데이터를 처리할 수 있는 기능을 갖출 수 있다. 본 논문에서는 TS 다중화를 위한 기본 기능과 함께 스플라이싱 및 PSIP 스트리밍 등의 보조 기능을 수용할 수 있는 재다중화기의 구조를 제안한다.

• The Journal of the Korea institute of electronic communication sciences
• /
• v.13 no.1
• /
• pp.9-14
• /
• 2018

This study describes the design and implementation of IMUX(Input Multiplexer) for Satellite Communication. The IMUX unit for SHF band consists of Combine Filter, Power Splitter, Isolator and Channel Filter. Through the pre-simulation analysis of space environment, the possibility of the malfunction of equipment minimized and we designed a reliable IMUX through simulation for vibration analysis generated during the launch, and compared pre-simulation of main performance results to test results about main performances of IMUX after production.

• Journal of Digital Contents Society
• /
• v.18 no.5
• /
• pp.881-888
• /
• 2017

Logic design using multiplexer has been used as a useful method for design convenience and flexibility in structural digital system design. In this paper, we analyze the effect of don't care conditions on logic optimization in a multiplexer-based logic design, which was not discussed enough in the previous studies in multiplexer based logic design, and describe the use of don't care conditions for designing of a single multiplexer and multiple multiplexer-based logic design. Especially, the design method when the number of data input is not 2m (as the number of selection lines is m) is considered. We also describe how to apply the proposed technique to the digital logic design education in conjunction with microprocessor design using Arduino which is widely used in creative engineering education recently.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.11 no.3
• /
• pp.179-196
• /
• 1986

In this paper, the peformance of a statistical packet voice/data multiplexer is studied. In ths study we assume that in the packet voice/data multiplexer two separate finite queues are used for voice and data traffics, and that voice traffic gets priority over data. For the performance analysis we divide the output link of the multiplexer into a sequence of time slots. The voice signal is modeled as an (M+1) - state Markov process, M being the packet generation period in slots. As for the data traffic, it is modeled by a simple Poisson process. In our discrete time domain analysis, the queueing behavior of voice traffic is little affected by the data traffic since voice signal has priority over data. Therefore, we first analyze the queueing behavior of voice traffic, and then using the result, we study the queueing behavior of data traffic. For the packet voice multiplexer, both inpur state and voice buffer occupancy are formulated by a two-dimensional Markov chain. For the integrated voice/data multiplexer we use a three-dimensional Markov chain that represents the input voice state and the buffer occupancies of voice and data. With these models, the numerical results for the performance have been obtained by the Gauss-Seidel iteration method. The analytical results have been verified by computer simylation. From the results we have found that there exist tradeoffs among the number of voice users, output link capacity, voic queue size and overflow probability for the voice traffic, and also exist tradeoffs among traffic load, data queue size and oveflow probability for the data traffic. Also, there exists a tradeoff between the performance of voice and data traffics for given inpur traffics and link capacity. In addition, it has been found that the average queueing delay of data traffic is longer than the maximum buffer size, when the gain of time assignment speech interpolation(TASI) is more than two and the number of voice users is small.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.18 no.6
• /
• pp.889-894
• /
• 1993

Asychronous Transfer Mode (ATM) provides the means to transport different types of bursty traffic such as voice, video, and bulk data. To handle more efficiently the traffic sources and to increase the bandwidth utilization as much as possible, flexible statistical multiplexing schemes must be adopted for the ATM networks. This paper presents an efficient computational procedure to calculate the queue state distribution in a finite buffer queueing system with a number of independent input sources, and the cell loss probability is exactly calculated with the use of this recursion computation method. The cell loss probability is related to a ATM multiplexer with a homogeneous ON-OFF source is also investigated through numerical examples.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.9 no.3
• /
• pp.587-594
• /
• 2005

In the paper, after we propose a viterbi decoder which has multiple buffering and parallel processing decoding scheme through expanding time-divided imput signal, and map a FPGA, we implement a channel coding system together with PC-based software. Continuous input signal is buffered as order of decoding length and is parallel decoded using a high speed cell for viterbi decoding. Output data rate increases linearly with the cell formed the viterbi decoder, and flexible operation can be satisfied by programming controller and modifying input buffer. The tell for viterbi decoder consists of HD block for calculating hamming distance, CM block for calculating value in each state, TB block for trace-back operation, and LIFO. The implemented cell of viterbi decoder used 351 LAB(Logic Arrary Block) and stably operated in maximum 139MHz in APEX20KC EP20K600CB652-7 FPGA of ALTERA. The whole viterbi decoder including viterbi decoding cells, input/output buffers, and a controller occupied the hardware resource of $23\%$ and has the output data rate of 1Gbps.

• Journal of the Korea Computer Industry Society
• /
• v.2 no.9
• /
• pp.1225-1232
• /
• 2001

In this paper, we investigate the scheduling algorithm of router system for Internet services on large scale ATM networks based on the quality-of-service(QoS) level of the input source traffics. We suggest an approprite scheduling algorithm in order to satisfy their QoS requirements. For this purpose, we first study the service requirements of the multiplexer in Internet. Second, we suggest functional architecture of the multiplexer for real time services and the scheduling algorithm to satisfy various QoS requirements. Finally, the performance measures of interest, namely steady-state average delay time and fairness of network resources, are discussed by simulation results.

• Journal of the Korean Institute of Telematics and Electronics
• /
• v.21 no.5
• /
• pp.79-89
• /
• 1984

In this paper we present development of microprocessor-based 8-channel statistical multiplexer (SMUX). The hardware design includes one Z-80A CPU board with the clock rate of 4 MHz, one 16 Kbyte ROM board for program storage, one 16 Kbyte dynamic RAM board and three I/O boards, all connected through an S-100 compatible tristate bus. The SMUX can presently multiplex 8 channels with data rates ranging 50 bps to 9600 bps, but can be reduced to accommodate 4 channels by having a slight modification of software and removing one terminal I/O board. The system specifications meet CCITT recommendations X.25 link level, V.24, V.28, X.3 and X.28. Significant features of the SMUX are its capability of handling 4 input codes (ASCII, EBCDIC, Baudot, Transcode), the use of a dynamic buffer management algorithm, a diagnostic facility, and the efficient use of a single CPU for all system operation. Throughout the paper, detailed explanations are given as to how the hardware and software of the SMUX system have been designed efficiently.

• Journal of the Institute of Electronics Engineers of Korea TC
• /
• v.39 no.3
• /
• pp.125-131
• /
• 2002

In this paper, a new concatenation scheme of serial concatenated convolutional codes is proposed and the performance analyzed. In the proposed scheme, each of information and parity bits of outer code is entered into inner code through interleaver and deinterleaver. Therefore, the interleaver size is same as the length of input frame. Since the interleaver size of proposed type is reduced to half of the conventional Benedetto type, the interleaver delay time required for iterative decoding is reduced. In addition the multiplexer and demultiplexer are not used in the decoder of the proposed type, the complexity of decoder can be also reduced. As results of simulation, the performance of proposed type shows the better error performance as compared to that of the conventional Benedetto type in case of the same interleaver size. And it can be observed that the difference of BER performance is increased with the increase of Eb/No. In case of the same length of input frame, the proposed type shows almost same performance with Benedetto type despite that the interleaver size is reduced by half.