• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2003.10a
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• pp.373-376
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• 2003

This paper presents a new, three-dimensional round-robin scheduler that provides high throughput and fair across in an advanced input-queued packet switch using shared input buffers. We consider an architecture in which each input port group shares a common buffer and maintains a separate queue for each output, which is ratted the distributed common input buffer switch. In an NxN switch, our scheduler determines which queue in the total MxN input queues is served during each time slot where M is the number of common buffers. We suppose that each common buffer has K input ports and K output ports, and manages N output queues. The 3DRR scheduler determines MxK queues in every K(M) cycle when $K\geq$M (K$\leq$M), and provides massively parallel processing for the applications of high-speed switches with a large number of ports. The 3-DRR scheduler can be implemented using duplicated simple logic components allowing very high-speed implementation.

• Journal of the Korean Institute of Telematics and Electronics S
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• v.36S no.2
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• pp.19-27
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• 1999

This paper propose a contention resolution policy featuring dynamic change of the threshold for the occupancy of the input buffer for an input buffering ATM switching architecture and its hardware implementation strategy. The strategy is provided with the aim of the simple structure that achieves the reduction of the signal path and the power consumption. The threshold is changed dynamically every time slot based both the arrived of cells and the cell service resulting from the contention resolution. The performance on the cell loss of the proposed policy is performed and compared with the conventional policy under the diverse traffic conditions through both the analysis based ont the Markov chain and the simulation.

• Journal of KIISE:Information Networking
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• v.29 no.6
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• pp.738-748
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• 2002

In this paper, a performance evaluation model of the Multistage Interconnection Network(MIN) with the multiple-buffered crossbar switches is Proposed and examined. Buffered switch technique is well known to solve the data collision problem of the MIN. The proposed evaluation model is developed by investigating the transfer patterns of data packets in a switch with output-buffers. The performance of the multiple-buffered${\alpha}{\times}{\alpha}$ crossbar switch is analyzed. Steady state probability concept is used to simplify the analyzing processes, Two important parameters of the network performance, throughput and delay, are then evaluated, To validate the proposed analysis model, the simulation is carried out on a Baseline network that uses the multiple buffered crossbar switches. Less than 2% differences between analysis and simulation results are observed. It is also shown that the network performance is significantly improved when the small number of buffer spaces is given. However, the throughput elevation is getting reduced and network delay becomes increasing as more buffer spaces are added in a switch.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.24 no.12A
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• pp.1910-1916
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• 1999

This paper suggested to solve ATM switch performance and service rate which was input buffer managed scheme in ATM network with burst traffic characteristics, For this purpose, ATM multiplexer is prepared before sending for handling burst random input traffic to multiplex and then sort based on cell inter-arrival time and cell processing due time which had been marked after that. The server looks for cell header with the most shortest due time and sends it, thus it is satisfied that real time traffic for instance CBR and rt-VBR was guaranteed cell processing time to send fast than non real time traffic. For analysis of ATM switch performance with cell processing due time and priority, each output port has divided into four different virtual buffer and each buffer has assigned different cell inter-arrival time and processing due time according to ATM Forum for example CBT/rt-VBR, nrt-VBR, ABR and UBR and showed it’s optimal service parameters then analyzed service rate behaviors according to each traffic characteristics.

• Journal of KIISE:Information Networking
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• v.34 no.3
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• pp.193-202
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• 2007

In this paper, a performance evaluation model of the Multistage Interconnection Network(MIN) with the multiple-buffered crossbar switches under Hot-spot environment is proposed and examined. Buffered switch technique is well known to solve the data collision problem of the MIN. The proposed evaluation model is developed by investigating the transfer patterns of data packets in a switch. The performance of the multiple-buffered $a{\times}a$ crossbar switch is analyzed. Steady state probability concept is used to simplify the analyzing processes. Two important parameters of the network performance, throughput and delay, are then evaluated. To validate the proposed analysis model, the simulation is carried out on a Baseline network that uses the multiple buffered crossbar switches. Less than 2% differences between analysis and simulation results are observed. It is also shown that the network performance is significantly improved when the small number of buffer spaces is given. However, the throughput elevation is getting reduced and network delay becomes increasing as more buffer spaces are added in a switch.

• Proceedings of the Korean Information Science Society Conference
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• 1999.10c
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• pp.411-413
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• 1999

본 논문에선느 ATM 통신망을 위한 여러 ATM 스위치 모델들 중에서, 내부적으로 블록킹(blocking)이 없고 입출력 단에 각각 버퍼가 할당되어 있는 입출력 버퍼형 교환기에 대하여 연구하였다. 기존에서 스위치 스피드-업(Switch Speed-up) 기법하에서 주로 연구가 이루어졌다. 따라서, 본 논문에서는 유니폼 트래픽하에서 Output-port Expansion 기법을 사용한 귀환.손실 모드 및 하이브리드 모드하에서의 셀 손실률을 비교 분석하였다. Output-port Expansion 기법은, 한 타임 슬롯동안에 입력포트 당 하나의 셀만 교환되며, 만약 하나 이상의 셀들이 같은 출력포트로 향하면, 최대 교환되는 셀 수를 K(Output-port Expansion Ratio)개로 제한하는 방식이다. 유니폼 트래픽(uniform random traffic) 하에서 각 모드에 따른 셀 손실률을 비교 분석한 결과, 로드 0.9를 기점으로, 0.9이하의 로드에서는 하이브리드 모드가, 0.9이상의 로드에서는 손실모드가 가장 낮은 셀 손실률을 보인다.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.11 no.5
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• pp.782-787
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• 2000

The monolithic single-pole three-throw(SP3T) GaAs PIN diode switch circuit for the broadband and high power application was designed, fabricated and characterized. To improve the power handling capability, buffer layers of the diode employ both low temperature buffer and superlattice buffer. The diode show the breakdown voltage of 65V and turn-on voltage of 1.3V. The monolithic integrated switch employed microstrip lines and backside via holes for low-inductance signal grounding. The vertical epitaxial PIN structure demonstrated better microwave performance than planar type structures due to lower parasitics and higher quality intrinsic region. As the large signal characteristics of the fabricated SP3T MMIC switch, the insertion loss was measured less than 0.6dB and the isolation better than 50dB when the input power was increased from 8dBM to 32dBm at 14.5GHz.

• Journal of the Korea Society of Computer and Information
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• v.11 no.1 s.39
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• pp.157-165
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• 2006

This paper proposes a new output-buffered multicast ATM switch with tandem crosspoints switching fabric, named the MTCOS(Multicast Tandem Crosspoint Output-buffered Switch). The MTCOS consists of multiple simple crosspoint switch fabrics, named TCSF(Tandem Crosspoint Switch Fabric) , and concentrated output buffers for efficient multicasting. The TCSF resolves the cell delay deviation problem which the self-routing crossbar switches inherently have. Further, it offers multiple concurrent pathes from one input to multiple output ports. It also provides multi-channel switching by easy software configuration and has several desirable characteristics such as scalability, high Performance, and modularity. A shared traffic concentration and output queuing strategies of the MTCOS results in lower cell loss as well as lower cell delay time over a wide range of multicast traffic. Furthermore, it has lower hardware complexity than that of the SCOQ and Knockout multicast switch to achieve the same Knockout concentration rate as the conventional switches. It is shown that the proposed switch can be easily applied to design high performance for any multicast traffic by analytic analysis and computer simulation.

• Journal of Internet Computing and Services
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• v.3 no.3
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• pp.87-93
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• 2002

A complex network and a parallel computer are made up of interconnected switching units. The role of a switching unit is to set up a connection between an input port and an output port, according to the routing information. We proposed our switching network with a remodeled architecture is a newly modified Banyan network with eight input and output ports. We have analysed the maximum throughput of the revised switch. Our analyses have shown that under the uniform random traffic load, the FIFO discipline is limited to 70%, The switching system consists of an input control unit, a switch unit and an output control unit. Therefore the result of the analyses shows that the results of the networking simulation with the new switch are feasible and if we adopt the new architecture of the revised model of the Banyan switch, the hardware complexity can be reduced. The FIFO discipline has increased by about 11% when we compare the switching system with the input buffer system. We have designed and verified the switching system in VHDL using Max＋plusII. We also designed our test environment including micro computers, the base station, and the proposed architecture. We proposed a new architecture of the Banyan switch for BISDN networks and parallel computers.

• Electronics and Telecommunications Trends
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• v.15 no.2 s.62
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• pp.15-31
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• 2000

IP 패킷스위칭을 수행할 수 있는 WDM 기반의 대용량 광패킷스위칭 시스템을 위해 입력광 신호 속도 10Gb/s의 16 x 단위 스위치로 구성되는 출력 버퍼링 방식의 방송 및 선택형스위치 구조가 제안되었다. 기존의 광소자는 광특성 때문에 집적광 집적화 논리회로(PCL)의 제작이 쉽지 않았으나 최근 세계적으로 어레이형 집적화 광소자의 개발 추세가 급속도로 진전되고 있어 대용량의 광교환기 시스템 구조는 기존의 교환기 시스템과 유사한 형태 및 구조가 가능하다.