• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2018.05a
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• pp.501-502
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• 2018

Traditional miniature micro-controllers focus on communication only because of memory capacity is low due to small size. Due to this, it is difficult to mount the UI for user convenience in the control system and a lot of functions cannot be added. To solve this problem, this paper proposes a weight reduction and encoding method for the control system. In addition, it is increased user convenience by overcoming the problem of difficulty in Korean system in the existing system. Also, we can add various functions to the memory space secured by system weight reduction.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.17 no.4
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• pp.229-235
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• 2024

Recent years have seen active research on methods for efficiently processing and interpreting large volumes of data in the fields of artificial intelligence and machine learning. One of these data processing technologies, Vector Symbolic Architecture (VSA), offers an innovative approach to representing complex symbols and data using high-dimensional vectors. VSA has garnered particular attention in various applications such as natural language processing, image recognition, and robotics. This study quantitatively evaluates the characteristics and performance of VSA methodologies by applying five VSA methodologies to the MNIST dataset and measuring key performance indicators such as encoding speed, decoding speed, memory usage, and recovery accuracy across different vector lengths. BSC and VT demonstrated relatively fast performance in encoding and decoding speeds, while MAP and HRR were relatively slow. In terms of memory usage, BSC was the most efficient, whereas MAP used the most memory. The recovery accuracy was highest for MAP and lowest for BSC. The results of this study provide a basis for selecting appropriate VSA methodologies depending on the application area.

• The KIPS Transactions:PartD
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• v.18D no.1
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• pp.35-44
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• 2011

Memory errors can cause not only program malfunctions but also even unexpected system halt. Though a programmer checks memory errors, some memory errors with low occurrence frequency are missed to detect. In this paper, we propose a method for effectively detecting such memory errors using instruction transition diagrams through analyzing assembly codes obtained by disassembling an executable file. Out of various memory errors, local memory return errors, null pointer access errors and uninitialized pointer access errors are targeted for detection. When applying the proposed method to various programs including well-known open source programs such as Apache web server and PHP script interpreter, some potential memory errors are detected.

• The Journal of Bigdata
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• v.4 no.2
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• pp.35-45
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• 2019

Recently, the damage with social cost of malicious comments is increasing. In addition to the news of talent committing suicide through the effects of malicious comments. The damage to malicious comments including abusive language and slang is increasing and spreading in various type and forms throughout society. In this paper, we propose a technique for detecting abusive language using a bi-directional long short-term memory neural network model. We collected comments on the web through the web crawler and processed the stopwords on unused words such as English Alphabet or special characters. For the stopwords processed comments, the bidirectional long short-term memory neural network model considering the front word and back word of sentences was used to determine and detect abusive language. In order to use the bi-directional long short-term memory neural network, the detected comments were subjected to morphological analysis and vectorization, and each word was labeled with abusive language. Experimental results showed a performance of 88.79% for a total of 9,288 comments screened and collected.

• Journal of KIISE:Computer Systems and Theory
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• v.27 no.2
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• pp.149-159
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• 2000

In this paper, we propose a new class of MIN (Multistage Interconnection Network) called SCMIN(ShortCut MIN) which can form a cheap and efficient packet switching interconnection network. SCMIN satisfies full access capability(FAC) and has multiple redundant paths between processor-memory pairs even though SCMIN is constructed with 2.5N-4 SEs which is far fewer SEs than that of MINs. SCMIN can be constructed suitable for localized communication by providing the shortcut path and multiple paths inside the processor-memory cluster which has frequent data communications. Therefore, SCMIN can be used as an attractive interconnection network for parallel applications with a localized communication pattern in shared-memory multiprocessor systems.

• Journal of KIISE:Databases
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• v.34 no.2
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• pp.109-118
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• 2007

Recently, flash memory is used to store data in mobile computing devices such as PDAs, SmartCards, mobile phones and MP3 players. These devices need index structures like the B-tree to efficiently support some operations like insertion, deletion and search. The BFTL(B-tree Flash Translation Layer) technique was first introduced which is for implementing the B-tree on flash memory. Flash memory has characteristics that a write operation is more costly than a read operation and an overwrite operation is impossible. Therefore, the BFTL method focuses on minimizing the number of write operations resulting from building the B-tree. However, we indicate in this paper that there are many rooms of improving the performance of the I/O cost in building the B-tree using this method and it is not practical since it increases highly the usage of the SRAM memory storage. In this paper, we propose a BOF(the B-tree On Flash memory) approach for implementing the B-tree on flash memory efficiently. The core of this approach is to store index units belonging to the same B-tree node to the same sector on flash memory in case of the replacement of the buffer used to build the B-tree. In this paper, we show that our BOF technique outperforms the BFTL or other techniques.

• Proceedings of the Acoustical Society of Korea Conference
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• spring
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• pp.343-346
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• 1999

터보부호는 일반적으로 인터리버의 크기가 클수록 성능이 우수한 것으로 알려져 있는데 이동통신 시스템 등에서 음성 신호를 전송하는 경우 프레임의 크기 즉, 인터리버의 크기가 너무 작아서 성능의 저하가 생기게 되는 것은 당연한 원리이다. 본 논문에서는 터보부호의 복호시 3개의 직렬 MAP복호기를 제안하여 기존의 방식보다 메모리 수는 감소시키면서 음성의 기준인 S/N 2.0[dB]에서 BER $10^{-3}$의 성능을 제안한 알고리즘을 통해 살펴본다. 모의실험결과, 부호율 1/3 , 반복복호의 수 5, 생성부흐 다항식 G=(7, 5)일 때 IS-95[9]에서 사용되고 있는 프레임과 같은 크기의 인터리버인 프레임 24인 경우 $10^{-2}$, 프레임 192인 경우 $10^{-3}$ 정도 값을 얻었다.

• The Journal of Society for e-Business Studies
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• v.12 no.1
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• pp.25-40
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• 2007

As memory-extended RFID tags are recently developed, various types of item identification structures can be stored in the tags. In this paper, we propose a new national product identifier(NPI) which accepts not only ISO item identification standards but also the memory capacity of ISO tags. First of all, item identification structures of ISO/IEC 15459 and EPC, and memory structures of ISO/IEC 18000-6C and EPC tags are analyzed. Based on these analyses, the NPI currently used is analyzed and its problems are described from the viewpoint of standardization. To overcome the problems, a new NPI structure suitable for ISO/IEC 15459 is proposed. Finally, data related to the NPI is designed for encoding to tags.

• Proceedings of the Korean Information Science Society Conference
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• 2000.10c
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• pp.609-611
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• 2000

CC-NUMA 시스템은 SMP 시스템의 장점인 프로그래밍의 편리함, 작업 환경의 유연함 및 관리의 용이함 등을 유지하는 한편, SMP의 단점이었던 확장성까지 제공한다. 더욱이 메모리 장벽 즉 급격히 빨라지는 프로세서의 처리 속도에 비해 메모리의 속도는 거의 변화가 없음으로 인하여 야기되는 문제를 극복할 수 있는 구조적인 대안으로 각광받고 있다. 이러한 CC-NUMA 시스템은 노드간의 논리적인 거리가 길기 때문에 프로세싱 노드간의 통신이 시스템의 성능에 영향을 미치는 가장 핵심 요소가 된다. 따라서 노드간의 통신을 최소화 해주기 위한 노력으로 각 노드에 장착되어지는 원격 캐쉬의 중요성이 강조된다. 본 논문에서는 CC-NUMA 시스템에서는 노드간 데이터 통신의 유형을 파악하고, 원격 캐쉬의 블록 사이즈에 따른 이들의 발생횟수의 변화를 분석하였다. 인스트럭션 시뮬레이터인 CacheMire와 II 벤치마크 중 하나인 FFT를 이용하여 실행-구동 시뮬레이션을 통해 원격캐쉬 블록의 크기가 증가할수록 노드간 통신의 횟수는 물론 전송되는 데이터의 절대적인 양이 감소한다는 사실을 알 수 있었다.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.30 no.6A
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• pp.526-534
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• 2005

This paper presents the structure and function of the system which automatically generates embedded processor cores using the SMDL. Accepting processor description in the SDML, the proposed system generates the processor core, consisting of the pipelined datapath and memory modules together with their control unit. The generated cores support muti-cycle instructions for proper handling of memory accesses, and resolve pipeline hazards encountered in the pipelined processors. Experimental results show the functional accuracy of the generated cores.