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Construction of an Automatic Generation System of Embedded Processor Cores  

Cho Jae-Bum (서강대학교 전자공학과 CAD & Embedded System 연구실)
You Yong-Ho (서강대학교 전자공학과 CAD & Embedded System 연구실)
Hwang Sun-Young (서강대학교 전자공학과 CAD & Embedded System 연구실)
Publication Information
The Journal of Korean Institute of Communications and Information Sciences / v.30, no.6A, 2005 , pp. 526-534 More about this Journal
Abstract
This paper presents the structure and function of the system which automatically generates embedded processor cores using the SMDL. Accepting processor description in the SDML, the proposed system generates the processor core, consisting of the pipelined datapath and memory modules together with their control unit. The generated cores support muti-cycle instructions for proper handling of memory accesses, and resolve pipeline hazards encountered in the pipelined processors. Experimental results show the functional accuracy of the generated cores.
Keywords
MDL; Automatic Generation; Embedded Core; ASIP;
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1 R. Gonzalez 'Xtensa : A Configurable and Extensible Processor' IEEE Micro, Magazine Vol. 20, No.2, pp. 60-70, March/April 2000
2 P. Marwedel and G. Goossens, 'Code Generation for Embedded Processors,' Kluwer Academic Publishers, pp. 138-152, 1995
3 O. Schliebusch et aI, 'A Novel Methodology for the Design of Application-Specific Instruction- Set Processors (ASIPs) Using a Machine Description Language', IEEE Transactions on, CAD of Int. Circuits and Systems, Vol. 20, No. 11, pp. 1338- 1354 Nov. 2001   DOI   ScienceOn
4 S. Furber 'ARM System-on-chip Architecture', Addison-Wesley, 2000
5 ARM, 'ARM7TDMI Technical Reference Manual (rev 3)', 2001
6 N. Dutt and K. Choi, 'Configurable Processor for Embedded Computing', IEEE Computer, Vol. 36, No.1, pp. 120-123, Jan. 2003
7 Y. Kim, H. Lee, and S. Hwang, 'An Interconnect Allocation Algorithm for Performance-driven Datapath Synthesis', Journal of Circuits, Systems, and Computers, Vol. 7, No.4. pp. 403-423 Sept. 1996
8 G. Kane, MIPS RISC Architecture, Prentice-Hall, 1998
9 A. Fauth, M. Fredericks, and A. Knoll, 'Generation of Hardware Machine Models from Instruction Set Descriptions', in Proc. IEEE Workshop VLSI Signal Processing, Veldhoven, Netherlands, pp. 242-250, Oct. 1993
10 J. Hennessy and D. Patterson, 'Computer Architecture : A Quantitative Approach', Morgan Kaufmann Publishers Inc., 1990
11 H. Lee and S. Hwang 'Design of a High-Level Synthesis System for Automatic Generation of Pipelined Datapath', Journal of KITE, Vol. 31-A, No.4, pp. 53-67, March 1994
12 Motorola, 'DSP56000 : 24-BIT Digital Signal Processor Family Manual', 1995
13 P. Mishra, A. Kejariwal, and N. Dutt, 'Rapid Exploration of Pipe lined Processors through Automatic Generation of Synthesizable RTL Model', in Proc. IEEE Int. Workshop on Rapid System Prototyping, San Diego, CA, pp. 226-232, June 2003
14 P. Kogge 'The Architecture of Pipelined Computers', Hemisphere Pub. Co., 1981
15 M. Itoh et al. 'Synthesizable HDL Generation for Pipelined Processors from a Micro-Operation Description' IEICE Trans., Vol. E83-A, No.3, pp. 394-400, March 2000
16 최기영, 조영철, 'SoC 설계방법의 최근 동향', 전자공학회지, 30권 9호, 2003년 9월, pp. 17-27
17 ARM, 'ARM922T Technical Reference Manual (rev 0)', 2001