• Journal of the Korea Institute of Information and Communication Engineering
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• v.17 no.1
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• pp.158-165
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• 2013

In this paper, a new circuit topology of an ultra-wideband (UWB) 3.1-10.6GHz CMOS low noise amplifier is presented. The proposed UWB low noise amplifier is designed utilizing RC feedback and LC filter networks which can provide good input impedance matching. In this design, the current-reused topology is adopted to reduce the power consumption and the inductor-peaking technique is applied for the purpose of bandwidth extension. The performance results of this UWB low noise amplifier simulated in $0.18-{\mu}m$ CMOS process technology exhibit a power gain of 14-14.9dB, an input matching of better than -10.8dB, gain flatness of 0.9dB, and a noise figure of 2.7-3.3dB in the frequency range of 3.1-10.6GHz. In addition, the input IP3 is -5dBm and the power consumption is 12.5mW.

• The Proceeding of the Korean Institute of Electromagnetic Engineering and Science
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• v.3 no.1
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• pp.11-19
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• 1992

To design of Ultra-wideband amplifier, we analyzed the inductor peaking to reduce the capacitance effect of GaAs MESFET in upper frequency edge. And we deduced an optimun inductor peaking element from transfer function of GaAs MESFET small-signal equivalent circut and realized the Feedback Amplifier Module (FAM) having flat gain. We design the imput and output impe dance matching networks by Real-Frequency Method. It show that the gain of designed amplifier has a 6.38dB with gain variation 0.56 at 0.1~12 GHz frequency gand by computer simu-lation.

• Proceedings of the IEEK Conference
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• 1999.06a
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• pp.305-308
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• 1999

In this paper, a transimpedance optical receiver based on PIN/P-HEMT with cascoded input stage and inductor peaking technique was designed for several giga bits optical communication. Analysis of the receiver shows that cascoded input stage with inductor peaking increase bandwidth without sacrificing low frequence gain. The receiver achieved a low noise characteristic and maximally flat frequence response. It is shown that the 3-dB bandwidth of the designed receiver is 8.3 ㎓ and input equivalent noise current is as low as 16pA/√Hz to 10㎓.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.19 no.11
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• pp.2238-2248
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• 1994

In this paper, we analyze a Microwave Amplifier Ultra-Wideband charateristic to apply Multi-Giga b/s optical receiver preamplifier in high speed optical communication system. To obtain frequency expanding effect. we analyze the frequency gain degradation effects of capacitances in the GaAs MESFET small-signal equivalent circuit and design Feedback amplifier Module(FAM) which has inductor peaking elements to compensate its effects and to expand frequency band. We derive optimum inductor peaking values in order to get flat gain in frequency band. The input and the output impedances of FAM are matched by Real Frequency Method and we design one and two stage ultra wideband microwave amplifier. With simulation results, it show $6.36\sim6.86dB$ and $9.1\sim10.3dB$ gains and execllent gain flatness in $0.5\sim12GHz$ respectively.

• Journal of the Institute of Electronics and Information Engineers
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• v.54 no.1
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• pp.33-38
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• 2017

In this paper, a 4-channel common-cathode VCSEL diode driver array with 3.125 Gb/s per channel operation speed is realized. In order to achieve faster speed of the switching main driver with relatively large transistors, the transmitter array chip consists of a pre-amplifier with active inductor stage and also an input buffer with modified equalizer, which leads to bandwidth extension and reduced current consumption. The utilized VCSEL diode provides inherently 2.2 V forward bias voltage, $50{\Omega}$ resistance, and 850 fF capacitance. In addition, the main driver based upon current steering technique is designed, so that two individual current sources can provide bias currents of 3.0 mA and modulation currents of 3.3 mA to VCSEL diodes. The proposed 4-channel VCSEL driver array has been implemented by using a $0.11-{\mu}m$ CMOS technology, and the chip core occupies the area of $0.15{\times}0.18{\mu}m^2$ and dissipates 22.3 mW per channel.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.39B no.7
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• pp.440-448
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• 2014

A $4{\times}10$ Gb/s Transimpedance Amplifier (TIA) array is implemented in $0.13{\mu}m$ CMOS process technology, which will be used in the receiver of TWDM-PON system. A technology for bandwidth enhancement of a given $4{\times}10$ Gb/s TIA presented under inductor peaking technology and a single 1.2V power supply based low voltage design technology. It achieves 3 dB bandwidth of 7 GHz in the presence of a 0.5 pF photodiode capacitance. The trans-resistance gain is $50dB{\Omega}$, while 48 mW/ 1channel from a 1.2 V supply. The input sensitivity of the TIA is -27 dBm. The chip size is $1.9mm{\times}2.2mm$.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.42 no.8 s.338
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• pp.53-60
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• 2005

Recently, sub-micron CMOS technologies have taken the place of III-V materials in a number of areas in integrated circuit designs, in particular even for the applications of gjgabit optical communication applications due to its low cost, high integration level, low power dissipation, and short turn-around time characteristics. In this paper, a four-channel transimpedance amplifier (TIA) array is realized in a standard 0.35mm CMOS technology Each channel includes an optical PIN photodiode and a TIA incorporating the fully differential regulated cascode (RGC) input configuration to achieve effectively enhanced transconductance(gm) and also exploiting the inductive peaking technique to extend the bandwidth. Post-layout simulations show that each TIA demonstrates the mid-band transimpedance gain of 59.3dBW, the -3dB bandwidth of 2.45GHz for 0.5pF photodiode capacitance, and the average noise current spectral density of 18.4pA/sqrt(Hz). The TIA array dissipates 92mw p in total from a single 3.3V supply The four-channel RGC TIA array is suitable for low-power, high-speed optical interconnect applications.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.37 no.3
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• pp.34-38
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• 2000

This paper describes design, fabrication, and performance of an ultra-high-speed and low-noise MMIC (Monolithic Microwave Integrated Circuit) preamplifier for a 10 Gb/s optical receiver. The transimpedance type 3-stage MMIC preamplifier for ultra-high-speed and low-noise was designed using an AlGaAs/InGaAs/GaAs P-HEMTs(Pseudomorphic High Electron Mobility Transistors) with 0.15${\mu}{\textrm}{m}$ length T-shaped gate. To obtain broadband characteristics, we used the inductor peaking technique, and the gate width was optimized for low noise performance. Measurements reveal that the fabricated preamplifier has the high transimpedance gain of 60 ㏈Ω and 9.15 ㎓ bandwidth with the noise figure of less than 3.9 ㏈.