• Proceedings of the Korea Information Processing Society Conference
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• 2013.11a
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• pp.977-979
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• 2013

본 논문은 스마트 폰 상의 SNS(Social Network Service)기반의 집단의 지식을 효율적으로 공유할 수 있도록 게임화(Gamification)전략을 도입한 질의응답 시스템을 제안한다. 질의응답 시스템은 신규 사용자 및 이미 많은 사용자가 있는 트위터와 페이스북 서비스에서 제공하는 API를 이용하여 사용자를 확보하고, 질문과 답변을 쉽게 할 수 있도록 한다. 또한 게이미피케이션 전략을 통해 사용자의 적절한 서비스 재 몰입루프를 형성한다. 따라서 제안된 시스템에 따라 서비스의 장기간 사용을 사용자에게 효율적으로 유도할 수 있다.

• New & Renewable Energy
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• v.20 no.2
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• pp.55-64
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• 2024

To ensure the frequency stability of wind power generation, we analyzedd the existing technology and proposedd a method for changing the gain value with respect to to the rotor speed by adding the MPPT reference value and output reference value that reflect the system frequency. The MPPT control and output were compared and calculated for performance verification. Subsequently, the application of the proposed algorithm led to an increased output when compared with that of the existing control method.

• The Journal of The Korea Institute of Intelligent Transport Systems
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• v.6 no.2
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• pp.34-44
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• 2007

Many urban cities deployed ITS technologies to improve the efficiency of traffic operation and management including a real-time franc control system (i.e., COSMOS). The system adopted loop detector system to collect traffic information such as volume, occupancy time, degree of saturation, and queue length. This paper investigated the applicability of detector information within COSMOS to represent the congestion level of the links. Initially, link travel times obtained from the field study were related with each of detector information. Results showed that queue length was highly correlated with link travel time, and direct link travel time estimation using the spot speed data produced high estimation error rates. From this analysis, a procedure was proposed to estimate congestion level of the links using both degree of saturation and queue length information.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.20 no.9
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• pp.967-973
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• 2009

In this paper, X-band satellite communication oscillator of double phase locked is implemented by constructing a couple of phased-locked loop, and then we have analyzed the phase noise of designed PLL-DRO. The designed phase-locked oscillator is consist of series feedback DRO, frequency divider, phase detector, loop filter and programmable PLL-IC. By dividing oscillation frequency of 12.6 GHz into two frequencies, it exhibits output power of 15.32 dBm at 6.3 GHz. Phase noises of implemented oscillator are -81 dBc/Hz@100Hz, -100.86 dBc/Hz@1 kHz, -111.12 dBc/Hz@10 kHz, -116 dBc/Hz@100 kHz and -140.49 dBc/Hz@1 MHz respectively. These indicate excellent stable operation of oscillator and very good phase noise characteristics.

• Journal of IKEEE
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• v.23 no.3
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• pp.800-804
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• 2019

This paper presents a dual-loop sub-sampling digital PLL for a 2.4 GHz IoT applications. The PLL initially performs a divider-based coarse lock and switches to a divider-less fine sub-sampling lock. It achieves a low in-band phase noise performance by enabling the use of a high resolution time-to-digital converter (TDC) and a digital-to-time converter (DTC) in a selected timing range. To remove the difference between the phase offsets of the coarse and fine loops, a phase offset calibration scheme is proposed. The phase offset of the fine loop is estimated during the coarse lock and reflected in the coarse lock process, resulting in a smooth transition to the fine lock with a stable fast settling. The proposed digital PLL is designed by SystemVerilog modeling and Verilog-HDL and fully verified with simulations.

• The Journal of the Korea Contents Association
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• v.10 no.3
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• pp.423-435
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• 2010

The number of professionals in the science and engineering fields decreases all over the world. Especially in Korea, the declining rate of both the laborable and economically active population, aging of the population at the fastest level, and the declining birth rate make it tougher to secure the core brains of the future. After speculation of all programs above, some common factors have been derived and every program appeared to have the support for each level of inducing, caring, and utilizing. And the means of support could be categorized into the financial, legal, and social aspects. Lastly, a logical tool called Systems Thinking has been applied to the FLS Conditions and the Brain Internalization Process to assure the efficacy and applicability of the models. This is to minimize any de facto side effects by analyzing all 'feedback loops' stemming from the models. And the 'causal loop diagrams' have been utilized to come with the complementary measures. Such series of verification could convince the virtue of the models. Governments and universities can make use of the FLS Conditions and the Brain Internalization Process so the policies or plans about the foreign brains can be built in a uniformized and consistent framework. I hope, as a result, the international competency of Korea to induce and utilize the foreign brains be raised with the constant and standardized formality.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.42 no.6
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• pp.23-36
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• 2005

PLLs have been widely used for many applications including communication systems. This paper presents a VCO with an improved negative skewed delay scheme and a PLL using this VCO. The proposed VCO and PLL are intended for replacing traditional LC oscillators and PLLs used in communication systems and other applications. The circuit designs of the VCO and PLL are based on 0.18um CMOS technology with 1.8V supply voltage. The proposed VCO employs subfeedback loops using pass-transistors and needs two opposite control voltages for the pass transistors. The subfeedback loops speed up oscillation depending on the control voltages and thus provide a high oscillation frequency. The two voltage controls have opposite frequency gain characteristics and result in low phase-noise. The 7-stage VCO in 0.18um CMOS technology operates from $3.2GHz\~6.3GHz$ with phase noise of about -128.8 dBc/Hz at 1MHz frequency onset. For 1.8V supply voltage, the current consumption is about 3.8mA. The proposed PLL has dual loop-filters for the proposed VCO. The PLL is operated at 5GHz with 1.8V supply voltage. These results indicate that the proposed VCO can be used for radio frequency operations replacing LC oscillators. The circuits have been designed and simulated using 0.18um TSMC library.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.12 s.354
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• pp.47-54
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• 2006

This work proposes a dual-channel 6b 1GS/s ADC for ultra wide-band communication system applications. The proposed ADC based on a 6b interpolated flash architecture employs wide-band open-loop track-and-hold amplifiers, comparators with a wide-range differential difference pre-amplifier, latches with reduced kickback noise, on-chip CMOS references, and digital bubble-code correction circuits to optimize power, chip area, and accuracy at 1GS/s. The ADC implemented in a 0.18um 1P6M CMOS technology shows a signal-to-noise-and-distortion ratio of 30dB and a spurious-free dynamic range of 39dB at 1GS/s. The measured differential and integral non-linearities of the prototype ADC are within 1.0LSB and 1.3LSB, respectively. The dual-channel ADC has an active area of $4.0mm^2$ and consumes 594mW at 1GS/s and 1.8V.

• Korean Journal of Materials Research
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• v.11 no.7
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• pp.615-621
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• 2001

We carried out the kinetic model calculations in order to estimate the nucleation rates for two kinds of half-loop dislocations in highly strained hetero-epitaxial growths; $60^{\circ}$dislocations and twinning dislocations. The surface defects and the stress concentration effects were considered in this model, and the remaining elastic strain of the epilayers with increasing film thickness was taken into account by using the modified Matthews' relation. The calculations showed that the stress concentration effect at surface imperfections is very important for describing the defect generation in highly mismatched epitaxial growth. This work also showed that the stress concentration effect determined the type of dislocation nucleating dominantly at early growth stages in accordance with our XTEM (cross-section transmission electron microscopy) defect observation.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.11
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• pp.79-85
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• 2004

A digitally-controlled analog-block inevitably undergoes the bang-bang oscillations which may cause a big amplitudes of the glitches if the oscillation occurs at the MSB transition points of a binary counter. The glitch results into the jitter noise for the case of the DLL. In this paper, we devise a new counter code that has the hysteresis in the bit transitions in order to prevent the transitions of the significant counter-bits at the locking state. The maximum clock jitter is simulated to considerably reduce over the voltage-temperature range guaranteed by specifications. The counter is employed to implement the high speed packet-base DRAM and contributes to the maximized valid data-window.