• Journal of Drive and Control
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• v.15 no.1
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• pp.28-37
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• 2018

When the wind speed rises above the rated wind speed, the produced power of the wind turbines exceeds the rated power. Even more, the excessive power results in the undesirable mechanical load and fatigue. A solution to this problem is pitch control of the wind turbines. This paper presents a systematic design method of a collective pitch controller for the wind turbines using a discrete fuzzy Proportional-Integral (PI) controller. Unlike conventional PI controllers, the fuzzy PI controller has variable gains according to its input variables. Generally, tuning the parameters of fuzzy PI controller is complex due to the presence of too many parameters strongly coupled. In this paper, a systematic method for the fuzzy PI controller is presented. First, we show the fact that the fuzzy PI controller is a superset of the PI controller in the discrete-time domain and the initial parameters of the fuzzy PI controller is selected by using this relationship. Second, for simplicity of the design, we use only four rules to construct nonlinear fuzzy control surface. The tuning parameters of the proposed fuzzy PI controller are also obtained by the aforementioned relationship between the PI controller and the fuzzy PI controller. As a result, unlike the PI controller, the proposed fuzzy PI controller has variable gains which allow the pitch control system to operate in broader operating regions. The effectiveness of the proposed controller is verified with computer simulations using FAST, a NREL's primary computer-aided engineering tool for horizontal axis wind turbines.

• The Transactions of the Korean Institute of Power Electronics
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• v.2 no.2
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• pp.29-34
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• 1997

In this paper, instantaneous controller of a single-phase PWM converter is realized using DSP. The stable PI gain of the input current and the DC link voltage control system is designed. The DC link voltage control system can be designed in continuous- time domain. But as for the input current control system, the descretizing effect cannot be ignored so it must be designed in descrete-time domain considering the calculation time. The capacitance estimating algorithm which can be acquired through the ripple voltage is proposed. By this algorithm the DC link capacitance can be estimated even under the transient state. Experimental results show the input power factor of 99.1% and the voltage variation rate of $\pm$5% according to the load variation.

• The Journal of the Korea institute of electronic communication sciences
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• v.16 no.3
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• pp.511-518
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• 2021

In order to obtain a good tracking performance of the motor, it is necessary to design a controller that can respond to a disturbance by including a disturbance observer. The disturbance observer of the motor is designed to estimate the load torque and the back electromotive voltage based on the first-order low-pass filter. A PI controller and an IP controller were designed to compare the correlation between the disturbance observer and the controller and to obtain improved control performance. To check the performance of the designed observer and the controller, it was applied to a 120 [W] class BLDC motor. As a result, overshoot is reduced, and it can be seen that the steady-state error converges to zero.

• Journal of the Korean Institute of Telematics and Electronics
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• v.17 no.6
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• pp.38-43
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• 1980

For linear discrete-time time-invariant multi-input mufti-output systems, a necessary condition which an optimal output Proportional feedback gains must satisfr is deiived. Quadratic performance index is used. The result is extended to the desi01 problem for determining optimal output proportional plus integral feedback gains. For illustration, an example problem is solved and discussed.

• The Journal of the Korea institute of electronic communication sciences
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• v.16 no.3
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• pp.503-510
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• 2021

This study intends to apply the mathematical method of fractional order differentiation to a controller that controls the response of the system. Therefore, we design integrator for the fractional index by converting it into discrete time to construct a controller. The IP controller composes an integral controller for errors and the proportional controller applies only the system output. The controller is designed by using the fractional order integrator to the integral controller of the IP controller. First, the performance of the PI controller and the IP controller is compared, and the designed controller is applied to the speed control of the motor. As a result, the motor output speed was uniformed and precise control performance could be obtained. It was confirmed that the speed error in the steady state is within 0.1 [%], and it has precise and uniform speed control performance without overshoot.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.21 no.12
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• pp.3235-3245
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• 1996

A DDFS(Direct Digital Frequency Synthesizer) used in spread spectrum communication systems must need fast switching speed, high resolution(the step size of the synthesizer), small size and low power. The chip has been designed with four parallel sine look-up table to achieve four times throughput of a single DDFS. To achieve a high processing speed DDFS chip, a 24-bit pipelined CMOS technique has been applied to the phase accumulator design. To reduce the size of the ROM, each sine ROM of the DDFS is stored 0-.pi./2 sine wave data by taking advantage of the fact that only one quadrant of the sine needs to be stored, since the sine the sine has symmetric property. And the 8 bit of phase accumulator's output are used as ROM addresses, and the 2 MSBs control the quadrants to synthesis the sine wave. To compensate the spectrum purity ty phase truncation, the DDFS use a noise shaper that structure like a phase accumlator. The system input clock is divided clock, 1/2*clock, and 1/4*clock. and the system use a low frequency(1/4*clock) except MUX block, so reduce the power consumption. A 107MHz DDFS(Direct Digital Frequency Synthesizer) implemented using 0.8.mu.m CMOS gate array technologies is presented. The synthesizer covers a bandwidth from DC to 26.5MHz in steps of 1.48Hz with a switching speed of 0.5.mu.s and a turing latency of 55 clock cycles. The DDFS synthesizes 10 bit sine waveforms with a spectral purity of -65dBc. Power consumption is 276.5mW at 40MHz and 5V.