• Journal of the Korea Society of Computer and Information
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• v.28 no.2
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• pp.69-75
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• 2023

Finite field arithmetic operations play an important role in a variety of applications, including modern cryptography and error correction codes. In this paper, we propose an efficient multiplication algorithm over finite fields using the Montgomery multiplication algorithm. Existing multipliers can be implemented using AND and XOR gates, but in order to reduce time and space complexity, we propose an algorithm using NAND and NOR gates. Also, based on the proposed algorithm, an efficient semi-systolic finite field multiplier with low space and low latency is proposed. The proposed multiplier has a lower area-time complexity than the existing multipliers. Compared to existing structures, the proposed multiplier over finite fields reduces space-time complexity by about 71%, 66%, and 33% compared to the multipliers of Chiou et al., Huang et al., and Kim-Jeon. As a result, our multiplier is proper for VLSI and can be successfully implemented as an essential module for various applications.

• Proceedings of the Korea Institutes of Information Security and Cryptology Conference
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• 1994.11a
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• pp.166-179
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• 1994

Diffie-Hellman 의 공개 키 암호 프로토콜이 제안된 이후 이산 대수 문제의 어려움이 프로토콜의 안전도와 깊이 연관되었다. 유한체를 이용한 암호 기법을 ElGamal 이 세웠으나, Index-Calculus 알고리듬에 의해 유한체위 에서 이산 대수 문제가 subexponential 알고리듬이되 어 ElGamal 기법의 안전도가 약해졌다. Nonsupersingular타원 곡선을 선택하여 유한체대신 ElGamal 암호 기법에 적용하면 안전한 암호 시스템을 설계할 수 있다. 이 논문에서는 콤퓨터 구현시 용이한 nonsupersingular 타원 곡선을 선택하는 방법, 유한체위에서의 연산, 평문을 타원 곡선의 원소로 임베드(Imbedding) 하는 방법 등 타원 곡선을 암호시스템에 적응하기 어려운 점들에 대한 해결 방법을 소개하고, 실제로 콤퓨터로 구현하여 그 실행 결과와 ElGamal 기법을 개선한 Schnorr 기법을 실행한 결과를 밝혔다.

• The Journal of the Korea institute of electronic communication sciences
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• v.7 no.1
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• pp.69-79
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• 2012

In this paper, we restrict the case as m odd, n=mk, and propose and explicitly exhibit the architecture of a new parallel multiplier over the field GF($2^m$) with a type k Gaussian period which is a subfield of the field GF($2^n$) implements multiplication using the parallel multiplier over the extension field GF($2^n$). The complexity of the time and area of our multiplier is the same as that of Reyhani-Masoleh and Hasan's multiplier which is the most efficient among the known multipliers in the case of type IV.

• Proceedings of the Korean Information Science Society Conference
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• 2002.04a
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• pp.892-894
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• 2002

본 논문은 유한 체 GF(/2 sup m/)상에서 A$B^2$연산을 위해 AOP(All One Polynomial)에 기반한 새로운 MSB(Most Significant bit) 유선 알고리즘을 제시하고, 제시한 알고리즘에 기반하여 병렬 입출력 세미시스톨릭 구조를 제안한다. 제안된 구조는 표준기저(standard basis)에 기반하고 모듈라(modoular) 연산을 위해 다항식의 계수가 모두 1인 m차의 기약다항식 AOP를 사용한다. 제안된 구조에서 AND와 XOR게이트의 딜레이(deray)를 각각 /D sub AND$_2$/와/D sub XOR$_2$/라 하면 각 셀 당 임계경로는 /D sub AND$_2$+D sub XOR/이고 지연시간은 m+1이다. 제안된 구조는 기존의 구조보다 임계경로와 지연시간 면에서 보다 효율적이다. 또한 구조 자체가 정규성, 모듈성, 병렬성을 가지기 때문에 VLSI 구현에 효율적이다. 더욱이 제안된 구조는 유한 체상에서 지수 연산을 필요로 하는 Diffie-Hellman 키 교환 방식, 디지털 서명 알고리즘 및 EIGamal 암호화 방식과 같은 알고리즘을 위한 기본 구조로 사용할 수 있다. 이러한 알고리즘을 응용해서 타원 곡선(elliptic curve)에 기초한 암호화 시스템(Cryptosystem)의 구현에 사용될 수 있다.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.13 no.2
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• pp.293-298
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• 2009

In this contribution, a 193-bit elliptic curve cryptography coprocessor was implemented on an FPGA board. Optimized algorithms and numerical expressions which had been verified through C program simulation, should be analyzed again with HDL (hardware description language) such as Verilog, so that the verified ones could be modified to be applied directly to hardware implementation. The reason is that the characteristics of C programming language design is intrinsically different from the hardware design structure. The hardware IP which was double-checked in view of hardware structure together with algoritunic verification, was implemented on the Altera CycloneII FPGA device equipped with ARM9 microprocessor core, to a real chip prototype, using Altera embedded system development tool kit. The implemented finite field calculation IPs can be used as library modules as Elliptic Curve Cryptography finite field operations which has more than 193 bit key length.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.36 no.1C
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• pp.14-21
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• 2011

Cryptographic protocols based on bilinear pairings provide excellent alternatives to conventional elliptic curve cryptosystems based on discrete logarithm problems. Through active research has been done toward fast computation of the bilinear pairings, it is still believed that the computational cost of one pairing computation is heavier than the cost of one ECC scalar multiplication. However, there have been many progresses in pairing computations over binary fields. In this paper, we compare the cost of BLS signature scheme with ECDSA with equvalent level of security parameters. Analysis shows that the cost of the pairing computation is quite comparable to the cost of ECC scalar multiplication for the case of binary fields.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.42 no.6 s.336
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• pp.67-74
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• 2005

Crypto-systems have difficulties in designing hardware due to the various standards. We propose a programmable and configurable architecture for cryptography coprocessors to accommodate various crypto-systems. The proposed architecture has a 32 bit I/O interface and internal bus width, and consists of a programmable finite field arithmetic unit, an input/output unit, a register file, and a control unit. The crypto-system is determined by the micro-codes in memory of the control unit, and is configured by programming the micro-codes. The coprocessor has a modular structure so that the arithmetic unit can be replaced if a substitute has an appropriate 32 bit I/O interface. It can be used in many crypto-systems by re-programming the micro-codes for corresponding crypto-system or by replacing operation units. We implement an elliptic curve crypto-processor using the proposed architecture and compare it with other crypto-processors

• Journal of the Korea Society of Computer and Information
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• v.17 no.3
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• pp.1-10
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• 2012

A low-complexity Multiplication over GF(2m) and multiplier circuit has been proposed by using cyclic-shift coefficients and the irreducible trinomial. The proposed circuit has the parallel input/output architecture and shows the lower-complexity than others with the characteristics of the cyclic-shift coefficients and the irreducible trinomial modular computation. The proposed multiplier is composed of $2m^2$ 2-input AND gates and m (m+2) 2-input XOR gates without the memories and switches. And the minimum propagation delay is $T_A+(2+{\lceil}log_2m{\rceil})T_X$. The Proposed circuit architecture is well suited to VLSI implementation because it is simple, regular and modular.

• Journal of IKEEE
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• v.22 no.3
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• pp.522-531
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• 2018

A public-key cryptography processor EC-RSA was designed, which integrates a 224-bit prime field elliptic curve cryptography (ECC) defined in the FIPS 186-2 as well as RSA with 2048-bit key length into a single hardware structure. A finite field arithmetic core used in both scalar multiplication for ECC and exponentiation for RSA was designed with 32-bit data-path. A lightweight implementation was achieved by an efficient hardware sharing of the finite field arithmetic core and internal memory for ECC and RSA operations. The EC-RSA processor was verified by FPGA implementation. It occupied 11,779 gate equivalents (GEs) and 14 kbit RAM synthesized with a 180-nm CMOS cell library and the estimated maximum clock frequency was 133 MHz. It takes 867,746 clock cycles for ECC scalar multiplication resulting in the estimated throughput of 34.3 kbps, and takes 26,149,013 clock cycles for RSA decryption resulting in the estimated throughput of 10.4 kbps.

• Proceedings of the Korea Institutes of Information Security and Cryptology Conference
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• 1992.11a
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• pp.131-138
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• 1992

공용키 암호법의 대표적인 것으로 El Gamal 암호법과 RSA 암호법이 있는데, RAS 암호법은 정수의 인수분해가 어렵다는 것에 안전성을 둔 반면에 El Gamal 암호법은 discrete logarithm을 푸는 것이 어렵다는데 안전성을 두고 있다. (6) 그런데 유한체상의 멱승과 곱셈이 효율적으로 수행이 된다면 El Gamal 암호법이 유용하다는 사살을 알게 되었다. 그런데 Copperxmith의 이산로그 알고리즘을 이용하면 n〉1000이 되어야 El Gamal 암호법이 안전성을 보장 받을 수 있으나 이 경우 복잡도의 증가로 인한 gate수의 급속한 증가로 고속연산전용 VLSI 설계시 어려움이 있다. (3) 그래서 본 논문은 복잡도를 줄일 수 있는 정규기저들의 탐색에 연구의 중점을 두었다.