• Review of KIISC
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• v.1 no.2
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• pp.50-59
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• 1991

• The Journal of the Korea institute of electronic communication sciences
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• v.12 no.4
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• pp.621-628
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• 2017

The efficiency of implementation of the arithmetic operations in finite fields depends on the choice representation of elements of the field. It seems that from this point of view normal bases are the most appropriate, since raising to the power 2 in $GF(2^n)$ of characteristic 2 is reduced in these bases to a cyclic shift of the coordinates. We, in this paper, introduce our algorithm to transform fastly the conventional bases to normal bases and present the result of H/W implementation using the algorithm. We also propose our algorithm to calculate the multiplication and inverse of elements with respect to normal bases in $GF(2^n)$ and present the programs and the results of H/W implementations using the algorithm.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.16 no.1
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• pp.143-152
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• 2012

In this paper hardware implementation of GF($2^{191}$) elliptic curve cryptographic coprocessor which supports 7 operations such as scalar multiplication(kP), Menezes-Vanstone(MV) elliptic curve cipher/decipher algorithms, point addition(P+Q), point doubling(2P), finite-field multiplication/division is described. To meet structure resistant against simple power analysis, the ECC processor adopts the Montgomery scalar multiplication scheme which main loop operation consists of the key-independent operations. It has operational characteristics that arithmetic units, such GF_ALU, GF_MUL, and GF_DIV, which have 1, (m/8), and (m-1) fixed operation cycles in GF($2^m$), respectively, can be executed in parallel. The processor has about 68,000 gates and its simulated worst case delay time is about 7.8 ns under 0.35um CMOS technology. Because it has about 320 kbps cipher and 640 kbps rate and supports 7 finite-field operations, it can be efficiently applied to the various cryptographic and communication applications.

• Journal of the Institute of Electronics and Information Engineers
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• v.53 no.2
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• pp.70-75
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• 2016

This paper proposes the constructing method of effective multiplier based on the finite fields in case of P=2. The proposed multiplier is constructed by polynomial arithmetic part, mod F(${\alpha}$) part and modular arithmetic part. Also, each arithmetic parts can extend according to m because of it have modular structure, and it is adopted VLSI because of use AND gate and XOR gate only. The proposed multiplier is more compact, regularity, normalization and extensibility compare with earlier multiplier. Also, it is able to apply several fields in recent hot issue IoT configuration.

• The Journal of the Korea institute of electronic communication sciences
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• v.9 no.8
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• pp.867-873
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• 2014

Since the computation of a multiplicative inverse using MONB includes many squarings and thus calculating inverse is expensive, we, in this paper, propose a low cost inverse algorithm requiring $nb(2^nm-1)+w(2^nm-1)-2$ multiplications and $2^n-1$ squarings to compute an inverse in $GF(2^{2^nm})^*$ using special normal basis over $GF(2^{2^n})$, and give some implementation results using the algorithm and, show that the timing results of our implementation is faster than that of Itoh et al.'s method.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.8 no.6
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• pp.1188-1193
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• 2004

So far, there have been grossly 3 types of studies on GF(2m) multiplier architecture, such as serial multiplication, array multiplication, and hybrid multiplication. Serial multiplication method was first suggested by Mastrovito (1), to be known as the basic CF(2m) multiplication architecture, and this method was adopted in the array multiplier (2), consuming m times as much resource in parallel to extract m times of speed. In 1999, Paar studied further to get the benefit of both architecture, presenting the hybrid multiplication architecture (3). However, the hybrid architecture has defect that only complex ordo. of finite field should be used. In this paper, we propose a novel approach on developing serial multiplier architecture based on Mastrovito's, by modifying the numerical formula of the polynomial-basis serial multiplication. The proposed multiplier architecture was described and implemented in HDL so that the novel architecture was simulated and verified in the level of hardware as well as software. The implemented GF(2m) multiplier shows t times as fast as the traditional one, if we modularized the numerical expression by t number of parts.

• Journal of the Korea Society of Computer and Information
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• v.6 no.3
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• pp.56-63
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• 2001

In this paper, The GF(216) multiplier using its subfields GF(24) is designed. This design can be used to construct a sequential logic multiplier using a bit-parallel multiplier for its subfield. A finite field serial multiplier using parallel multiplier of subfield takes a less time than serial multiplier and a smaller complexity than parallel multiplier. It has an advatageous feature. A feature between circuit complexity and delay time is compared and simulated using C language.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.2
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• pp.49-54
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• 2008

In cryptosystems based on finite fields, a modular multiplication operation is the most crucial part of finite field arithmetic. Also, in multipliers with resource constrained environments, bit-serial output structures are used in general. This paper proposes two efficient bit-serial output multipliers with the polynomial basis representation for irreducible trinomials. The proposed multipliers have lower time complexity compared to previous bit-serial output multipliers. One of two proposed multipliers requires the time delay of $(m+1){\cdot}MUL+(m+1){\cdot}ADD$ which is more efficient than so-called Interleaved Multiplier with the time delay of $m{\cdot}MUL+2m{\cdot}ADD$. Therefore, in elliptic curve cryptosystems and pairing based cryptosystems with small characteristics, the proposed multipliers can result in faster overall computation. For example, if the characteristic of the finite fields used in cryprosystems is small then the proposed multipliers are approximately two times faster than previous ones.

• Proceedings of the Korea Institutes of Information Security and Cryptology Conference
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• 1996.11a
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• pp.145-150
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• 1996

정보보호기법을 적용한 다양한 서비스의 구현에 있어서는 적용기법에서 채택한 암호학적 연산에 의해 그 실용성이 종속하게 되며 이러한 실용화를 위한 하드웨어 또는 소프트웨어적 구현기법에 관한 많은 연구가 진행되고 있다. 본 논문에서는 유한체 GF(2$^{m}$ )상에서의 역원계산을 효율적이며 신속하게 처리할 수 있는 방법에 관해서 다루고 있다. 본 논문에서 제안하는 방법은 정규기저를 이용하여 임의의 유한체위에 적용 가능하도록 설계된 기법이다. 본 논문에서의 제안 방법은 이미 알려진 Itoh의 방법보다 대부분의 정수에 대하여 효율적임을 보인다.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.4 no.2
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• pp.17-28
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• 1994

Diffic-Hellman의 공개키 암호 프로토콜이 제안된 이후 이산 대수 문제의 어려움이 프로토콜의 안전도와 깊이 연관되었다. 유한체를 이용한 암호 기법을 EIGamal 이 세웠으나, Index-Calculus 알고리듬에 의해 유한체위에서 이산 대수 문제가 subexponential 알고리듬이 되어 기법의 안전도가 약해졌다. Nonsupersingular 타원 곡선을 선택하여 유한체대신 EIGamal 암호 기법에 적용하면 안전한 암호 시스템을 설계할 수 있다. 이 논문에서는 컴퓨터 구현시 용이한 nonsupersingular 타원곡선을 선택하는 방법, 유한체위에서의 연산, 평문을 타원 곡선의 원소로 끼워넣기(imbedding) 하는 방법등 타원 곡선을 암호 시스템에 적용하기 어려운 점들에 대한 해결 방법을 소개하고, 실제로 EIGamal기법을 컴퓨터로 구현하여 그 실행 결과를 밝혔다.