• The Journal of the Acoustical Society of Korea
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• v.37 no.2
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• pp.110-117
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• 2018

In this paper, we propose a low delay window switching MDCT (Modified Discrete Cosine Transform) method for speech/audio coder. The window switching algorithm is used to reduce the degradation of sound quality in non-stationary trasient duration and to reduce the algorithm delay by using the low delay TDAC (Time Domain Aliasing Cancellation). While the conventional window switching algorithms uses overlap-add with different lengths, the proposed method uses the fixed overlap add length. It results the reduction of algorithm delay by half and 1 bit reduction in frame indication information by using 2 window types. We apply the proposed algorithm to G.729.1 based on MDCT in order to evaluate the performance. The propose method shows the reduction of algorithm delay by half while speech quality of the proposed method maintains same as the conventional method.

• Electrical & Electronic Materials
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• v.6 no.4
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• pp.330-338
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• 1993

Channel의 폭과 길이가 15 x 15.mu.m, 15 x 1.5.mu.m, 1.9 x 1.7.mu.m인 비휘발성 SNOSFET EEPROM 기억소자를 CMOS 1 Mbit 설계규칙에 의하여 제작하고 체널크기에 따른 $I_{D}$- $V_{G}$특성 및 스위칭 특성을 조사하여 비교하였다. 게아트에 전압을 인가하여 질화막에 전하를 주입시키거나 소거시킨 후 특성을 측정한 결과, 드레인전류가 적게 흐르는 저전도상태와 전류가 많이 흐르는 고전도상태로 되는 것을 확인하였다. 15 x 15.mu.m의 소자는 전형적인 long channel특성을 나타냈으며 15 x 1.5.mu.m, 1.9 x 1.7.mu.m는 short channel특성을 보였다. $I_{D}$- $V_{G}$ 특성에서 소자들의 임계 문턱전압은 저전도상태에서 $V_{W}$=+34V, $t_{W}$=50sec의 전압에서 나타났으며 메모리 윈도우 폭은 15 x 15.mu.m, 15 x 1.5.mu.m, 1.9 x 1.7.mu.m의 소자에서 각각 6.4V, 7.4V, 3.5V였다. 스위칭 특성조사에서 소자들은 모두 논리스윙에 필요한 3.5V 메모리 윈도우를 얻을 수 있었으며 논리회로설계에 적절한 정논리 전도특성을 가졌다.특성을 가졌다.다.다.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.42 no.8 s.338
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• pp.35-42
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• 2005

This paper describes novel flip-flops with improved robustness and reduced power consumption. Variable sampling window flip-flop (VSWFF) adjusts the width of the sampling window according to input data, providing robust data latching as well as shorter hold time. The flip-flop also reduces power consumption for higher input switching activities as compared to the conventional low-power flip-flop. Clock swing-reduced variable sampling window flip-flop (CSR-VSWFF) reduces clock power consumption by allowing the use of a small swing clock. Unlike conventional reduced clock swing flip-flops, it requires no additional voltage higher than the supply voltage, eliminating design overhead related to the generation and distribution of this voltage. Simulation results indicate that the proposed flip-flops provide uniform latency for narrower sampling window and improved power-delay product as compared to conventional flip-flops. To evaluate the performance of the proposed flip-flops, test structures were designed and implemented in a $0.3\mu m$ CMOS process technology. Experimental result indicates that VSWFF yields power reduction for the maximum input switching activity, and a synchronous counter designed with CSR-VSWFF improves performance in terms of power consumption with no use of extra voltage higher than the supply voltage.

• Journal of Korea Society of Industrial Information Systems
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• v.18 no.5
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• pp.81-92
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• 2013

The satellite includes many release mechanisms such as solar array deployment, antenna deployment, cover to protect contamination in scientific equipment, pyro value of the propulsion subsytem, and bypass device in Li-Ion cell module. A drive the initiators is a critical to the successful mission because the initiators of release mechanism driving by the pyrotechnic circuit is operated in single short. The pyrotechnic circuit has to provide switching network for safety. A typical switching network has defect consisting of high current rating fire switch to handle switching transient current during fire the initiator. The pyrotechnic circuit is required some form of power conditioning to reduce the peak power demanded from the bus if the initiators are to be fired from the main bus. This paper design a pyrotechnic circuit synchronized to the fire-command to activate the fire switch to overcome use high current rating fire switch to handle switching transient current during fire the initiator. The pyrotechnic circuit provides a current limited widow pulse for fire current synchronized to the fire-command to insure that fire switch will only carry the current but never switch it. The current limited widow pulse for fire current can be possible to use low current rating and light mass switch in switching network. The current limit function in the pyrotechnic circuit reduces supply voltage to initiator and provides the effect of power conditioning function to reduce peak bus power. The pyrotechnic circuit to apply satellite development on geostationary orbit is verified the function by test in development model.

• Proceedings of the Acoustical Society of Korea Conference
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• 1998.06e
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• pp.23-26
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• 1998

This paper presents a technique to enhance TDAC in the AC-3 algorithm. To reduce block boundary noise without decreasing the performance of transform coding, new special window adopted. They improves the defect of the AC-3 algorithm that could not properly cancel aliasing in the tansient period. In addition, a fast MDCT calculation algorithm based on a fast Fourier Transform, is adopted.

• Proceedings of the KIPE Conference
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• 2004.07a
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• pp.325-329
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• 2004

본 논문은 하이브리드 전기자동차의 12V보조배터리 충전용 DC-DC 컨버터의 최적설계에 관한 것으로 하이브리드 전기자동차의 특성상 DC-DC 컨버터는 최대부하의 $30\%\~70\%$ 정도의 비교적 낮은 부하영역에서 주로 동작하므로 이에 따른 적절한 설계가 요구된다. 따라서 DC-DC 컨버터의 주 동작영역에서 효율이 높도록 주요 설계요소인 스위칭 주파수와 고주파 변압기의 누설인덕턴스를 적절히 선정하고 코아의 윈도우 면적을 최소화하는 최적설계에 관한 연구이다.

• The KIPS Transactions:PartC
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• v.8C no.6
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• pp.793-805
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• 2001

In the recent priority system, high-priority packet will be served first and low-priority packet will be served when there isn\`t any high-priority packet in the system. By the way, even high-priority packet can be blocked by HOL (Head of Line) contention in the input queueing System. Therefore, the whole switching performance can be improved by serving low-priority packet even though high-priority packet is blocked. In this paper, we study the performance of preemptive priority in an input queueing switch for high speed switch system. The analysis of this switching system is taken into account of the influence of priority scheduling and the window scheme for head-of-line contention. We derive queue length distribution, delay and maximum throughput for the switching system based on these control schemes. Because of the service dependencies between inputs, an exact analysis of this switching system is intractable. Consequently, we provide an approximate analysis based on some independence assumption and the flow conservation rule. We use an equivalent queueing system to estimate the service capability seen by each input. In case of the preemptive priority policy without considering a window scheme, we extend the approximation technique used by Chen and Guerin [1] to obtain more accurate results. Moreover, we also propose newly a window scheme that is appropriate for the preemptive priority switching system in view of implementation and operation. It can improve the total system throughput and delay performance of low priority packets. We also analyze this window scheme using an equivalent queueing system and compare the performance results with that without the window scheme. Numerical results are compared with simulations.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.7 no.2
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• pp.269-275
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• 2003

Polysilicon-oxide-nitride-oxide-silicon(SONOS) transistors were fabricated by using 0.35${\mu}{\textrm}{m}$ complementary metal-oxide-semiconductor(CMOS) process technology to realize a low voltage programmable flash memory. The thickness of the tunnel oxide, the nitride, and the blocking oxide were 2.4nm, 4.0nm, and 2.5nm, respectively, and the cell area of the SONOS memory was 1.32$\mu$$m^2$. The SONOS device revealed a maximum memory window of 1.76V with a switching time of 50ms at 10V programming, as a result of the scaling effect of the nitride. In spite of scaling of nitride thickness, memory window of 0.5V was maintained at the end of 10 years, and the endurance level was at least 105 program/erase cycles. Over-erase, which was shown seriously in floating gate device, was not shown in SONOS device.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.45 no.3
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• pp.51-58
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• 2008

This paper is a study of a prevention of power folding controller's thermal degradation. Power folding technology has been applied for many fields such as side rear vision mirror of vehicles, windshield wiper, antenna, power window. These controllers have been comprised with traditional DC moors, Switching electronic devices, and relays. But this methods have a limitation to overcome such problems of product reliability, endurance, noise margins. Therefore on this paper, to detect the movement of motor, sensing motor brush noise on a load sensing part has been used and controlling a precise RC timing control minimizes the thermal deterioration of motor. And using MOS FETs as a electronic switching device increases life-time and liability of control circuit. After testing such circuit and control method, repetition of operating time, cut-off time, wide operation voltage, power noise margin ware increased over eleven-fold.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.41 no.9
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• pp.73-80
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• 2004

In this paper, we present the cell resequencing buffer to solve the cell sequence integrity problem of the Cyclic banyan network that is a high-performance fault-tolerant cell switch. By offering multiple paths between input ports and output ports, using the deflection self-routing, the Cyclic banyan switch offer high reliability, and it also solves congestion problem for the internal links of the switch. By the way, these multiple paths can be different lengths for each other. Therefore, the cells departing from an identical source port and arriving at an identical destination port can reach to the output port as the order that is different from the order arriving at input port. The proposed cell resequencing buffer is a hardware sliding window mechanism. to solve such cell sequence integrity problem. To calculate the size of sliding window that cause the prime cost of the presented device, we analyzed the distribution of the cell delay through the simulation analyses under traffic load that have a nonuniform address distribution that express tile Property of traffic of the Internet. Through these analyses, we found out that we can make a cell resequencing buffer by which the cell sequence integrity is to be secured, by using a, few of ordinary memory and control logic. The cell resequencing buffer presented in this paper can be used for other multiple paths switching networks.