• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.14 no.1
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• pp.37-42
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• 2021

This paper presents a jitter and phase noise characteristic improved phase-locked loop (PLL) with loop filter voltage detector(LFVD) and frequency voltage converter(FVC). Loop filter output voltage variation is determined through a circuit made of resistor and capacitor. The output signal of a small RC time constant circuit is almost the same as to loop filter output voltage. The output signal of a large RC time constant circuit is the average value of loop filter output voltage and becomes a reference voltage to the added LFVD. The LFVD output controls the current magnitude of sub-charge pump. When the loop filter output voltage increases, LFVD decreases the loop filter output voltage. When the loop filter output voltage decreases, LFVD increases the loop filter output voltage. In addition, FVC also improves the phase noise characteristic by reducing the loop filter output voltage variation. The proposed PLL with LFVD and FVC is designed in a 0.18um CMOS process with 1.8V power voltage. Simulation results show 0.854ps jitter and 30㎲ locking time.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.24 no.10A
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• pp.1507-1516
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• 1999

본 논문에서는 전력증폭기 선형화를 위한 Cartesian feedback 방식의 궤환 경로에서 발생하는 DC offset과 이득 및 위상 불일치를 자동적으로 보상하는 개선된 방식을 제안한다. Cartesian feedback에 의한 비선형 전력증폭기 왜곡성분의 감쇠 정도는 시스템 루프의 이득, 대역폭, 시간지연에 의해 결정된다고 알려져 있다. 그러나 궤환 경로 각 소자에서 발생하는 DC offset과 이득 및 위상의 불일치로 인하여 송신기의 출력신호에 원하지 않는 반송파 성분과 이미지 신호가 발생하여 궤환보상의 효과가 반감되는 결과를 초래한다. 본 논문에서는 디지털 신호처리 시스템 구조에서 이진 검색 (binary search) 알고리즘을 이용하여 궤환 경로에서 발생하는 DC offset과 이득 및 위상 불일치를 자동적으로 보상하는 방식을 제안하고 컴퓨터 모의실험을 통하여 제안된 방식의 성능을 분석한다. 모의실험에서 고려된 방식에 비하여 동일한 정도의 DC offset과 이득 및 위상 불일치의 보상에 걸리는 시간을 평균적으로 40% 단축할 수 있었다.

• Journal of the Computational Structural Engineering Institute of Korea
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• v.12 no.2
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• pp.141-148
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• 1999

변위 근거 유한요소해석을 사용하는 대부분의 위상 최적화 기법은 요소의 안정성 부족으로 인하여 체스판 무늬가 주기적 형태로 반복하여 설계영역 내부에 나타난다. 본 연구에서는 선형요소를 이용하면서 최적화 알고리즘의 안정성에 영향을 주지 않고 간단하게 모든 최적화 알고리즘에 이용 가능한 체스판무늬 형성 방지책을 개발하였다. 본 연구의 체스판무늬 형성 방치책에서는 먼저 각 선형요소를 구성하는 절점들의 부치분율을 설계변수로 선정하고, 요소내부의 부피분율을 설계변수로 표현하기 위한 선형 보간함수로 선형요소들의 형상함수를 선정하였다. 그리고, 설계변수와 등가 재료상수와의 상관 관계식은 평균장 근사이론을 이용하여 균질화된 재료에 벌칙인자가 도입된 관계식을 이용하였다. 또한, 본 연구에서는 순차이차계획법인 PLBA 알고리즘을 이용하여 위상 최적화문제를 해석하였다.

• Journal of the Korean Society of Marine Environment & Safety
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• v.2 no.1
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• pp.1-10
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• 1996

초음파는 액체 및 고체의 매질 속에서도 그 전달 특성이 우수하여 수중 물체의 감지, 지질 조사 자원탐사뿐만 아니라, 의학 분야에서도 널리 사용되고 있다. 물체유동정보 측정방식에는 연속파를 이용한 도플러식과 펄스 신호를 이용한 도플러는 거리 분해능이 좋으므로 깊이에 따른 속도 정보를 쉽게 얻을 수 있는 장점이 있으나, 수신되는 도플러 신호가 탐촉자의 특성과 매질 속에서의 전파특성 등에 의하여 송신된 신호와 파형이 다르고 복잡한 주파수 특성을 가지므로 연속파에서와 같이 도플러 주파수를 직접 측정하기 곤란하다. 도플러 주파수를 검출하기 위하여 여러 방법이 개발되어 있으나, 측정거리와 측정속도의 제약과 더불어, 실시간(real time) 처리에 의한 분포적 측정이 어려운 실정이다. 본 연구에서는 시간 영역에서 국소 데이터를 이용하여 펄스 신호의 위상을 정의하고 실시간에서 펄스 신호를 위상으로 변환하는 신호 처리법을 제안하였다. 또한 이 신호 처리법을 응용하여 측정 범위의 위상 곡선에서 위상 차를 계산함으로써 평균 가속도와 유동속도정보를 분포적으로 얻을 수 있는 새로운 펄스 도플러 기법을 제안하였으며, 모델 신호를 만들어 제안된 방법의 유용성을 검토하였다.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.41 no.10
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• pp.27-33
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• 2004

In this paper, we present a carrier recovery circuit using the polarity-decision algorithm that recovers a phase and a frequency error simultaneously. The proposed algorithm catches a frequency error based on a differential of an angular velocity of the signal constellations. Using the differential of a phase error may compensate the frequency error. The symbol prediction method in the proposed algorithm accumulates the symbols, which makes easy to calculate a phase differential. The hardware size of the algerian is small since we use Q data or I only to get phase information. As a result, the algerian shows a pull-in range of normalized frequency error 0.5 under AWGN 15dB.

• Geophysics and Geophysical Exploration
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• v.13 no.4
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• pp.323-329
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• 2010

Three deconvolution methods were applied to stacked seismic data obtained to investigate gas-hydrates in the Ulleung Basin, East Sea: (1) minimum-phase spiking deconvolution, (2) minimum-phase spiking deconvolution using an averaged wavelet from all traces, and (3) deterministic deconvolution using a wavelet with phases computed from well-logs. We analyzed the resolving property of these methods for lithological boundaries. The first deconvolution method increases temporal resolution but decreases lateral continuity. The second method shows, in an overall sense, similar results to the spiking deconvolution using a minimum phase wavelet for each trace; however, it results in a more consistent and continuous bottom-simulating reflector (BSR) and better resolved sub-BSR reflectors. The results from the third method reveal more detailed internal structures of debris-flow deposits and increased continuity of reflectors; in addition, the seafloor reflection and the BSR appear to have changed to a zero-phase waveform. These properties help more precisely estimate the distribution and reserves of gas hydrates in the exploration area by improving analysis of facies and amplitude of the BSR.

• Journal of Advanced Navigation Technology
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• v.18 no.4
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• pp.341-346
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• 2014

This paper has presented the design and fabrication of phase correlator for wideband digital frequency discriminator (DFD) operating over the 6.0 to 18.0 GHz frequency range. Fabricated DFD phase correlator has been measured I or Q output signal, and analyzed frequency discrimination error. The operation of the proposed mixer type correlator has been analyzed by deriving some analytic equations. To design the phase correlator, this paper has modeled and simulated IQ mixer and 8-way power divider by using RF simulation tool. Designed phase correlator has fabricated and measured. The phase error and frequency discrimination error have been presented using by measured I and Q output signal. Over the 6.0~18.0 GHz range, the root mean square(RMS) phase error is $4.81^{\circ}$, RMS and frequency discrimination error is 1.49 MHz, RMS.

• Proceedings of the KSME Conference
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• 2000.04b
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• pp.661-666
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• 2000

Near-wake flow field of a circular cylinder is studied by means of a cinematic PIV system with high sampling rate and large internal memory block. Experiments are conducted in a closed-cycle water tunnel system and a cross-correlation algorithm in conjunction with FFT (Fast Fourier Transform) analysis and an offset correlation technique is used for vector processing. With the help of very high sampling frequency compared to the shedding frequency, it is possible to obtain phase-averaged information of the three-dimensional wake, even though the shedding is not forced but natural. Phase-locked vortical structures observed simultaneously from the spanwise and cross-stream planes are displayed in the wake-transition regime where fine-scale secondary vortices have a spanwise wavelength or around one diameter. Spatial relations and temporal evolutions of the primary Karman vortex and the secondary vortex are also discussed schematically.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.13 no.9
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• pp.907-915
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• 2002

In this paper, a compact digital phase shifter to be used an active phased array antenna system for satellite communications was proposed. The even and odd mode analysis for a given reflection-type phase shifter, which uses a folded hybrid coupler as a base element, was performed and the design parameters were derived. Also, to verify experimentally the electrical performances of the proposed structure, X-band 4-bit digital phase shifter was designed and fabricated using Teflon soft substrate $({\varepsilon}_r; =\;2.17)$. Its circuit size was less than 3.5 cm $\times$ 3.0 cm, and it exhibited at least 50 % size reduction as compared with the conventional unfolded configuration. The experimental results of the fabricated phase shifter showed that the average insertion loss and insertion loss variation were less than 3.5 dB, $\pm$ 0.6 dB within the operating band, 7.9 ~ 8.4 GHz, respectively. And, input and output return loss were more than 10 dB, respectively. Also, the phase response of the phase shifter showed 4-bit operation with $\pm$3$^{\circ}$ rms phase error.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.39 no.3
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• pp.158-164
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• 2002

2-6 GHz digital phase shifter module has been designed and fabricated. For the broadband operation and performance, MMIC phase shifter chip for phase shifter module was designed and fabricated by using the reflection-type circuits with Lange coupler. The fabricated phase shifter module shows 6.1$^{\circ}$RMS phase error, 13.5 dB maximum insertion loss, and 8 dB and 10 dB input and output return losses, respectively. Computer controlled measurement systems are realized in order to get the measured data of 32 phase states. The RMS insertion phase error and the average insertion loss deviation among 8${\times}$8 modules for the phased-array system are less than ${\pm}$0.5$^{\circ}$and ${\pm}$0.5 dB, respectively. The size of fabricated phase shifter module is 45 ${\times}$ 22.5 ${\times}$60㎣.