• Journal of Service Research and Studies
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• v.11 no.2
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• pp.118-130
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• 2021

This study designs and validates a greenhouse complex environmental control algorithm with a multi-phase processing scheme that can combine and control actuators according to the degree of change in the greenhouse environment. The composite environmental control system is a system in which the complex environmental controller analyzes the information detected by sensors and operates appropriately actuators to maintain the crop growth environment. A composite environmental controller directs control devices driving actuators through a composite environmental control algorithm, which calculates the values necessary for the operation of the control devices. Most existing algorithms carry out control procedures on a single phase by iteration cycle, which can cause abnormal changes in the greenhouse environment due to errors in output. The proposed algorithm distributes control procedures over multiple phases: environmental control, environmental control, and device operation, and every iteration cycle, detects environmental changes in the environmental control phase first, and then combines control devices that can control the environment in the environmental control phase, and finally, performs the controls to derive the actuators in the device operation phase. The proposed algorithm is designed based on the analysis of the relationship between greenhouse environmental elements and control devices deriving actuators. According to verification analysis, the multi-phase processing scheme provides room to modify or supplement the setting value and enables the control devices to reflect changes in the associated environmental components.

• Proceedings of the Korean Vacuum Society Conference
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• 2010.08a
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• pp.11-11
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• 2010

고도의 진공 환경을 요구하는 반도체 생산 라인에 적용되는 고진공 펌프는 주로 복합 분자펌프와 크라이오 펌프가 사용되고 있다. 이 중 크라이오 펌프는 극저온으로 냉각되는 냉각판에 기체 분자를 응축 또는 흡착시켜 기체를 제거하는 방식으로 복합 분자 펌프로 무게가 가볍고 증발 온도가 낮은 네온, 수소, 헬륨 기체 제거에 장점이 있다. 본 연구에서는 현재 상용화된 크라이오 펌프에 적용되는 GM 극저온 냉동기를 대체하기 위한 2단 GM형 맥동관 냉동기를 개발하여 기초 성능 시험을 수행하였다. 1단과 2단 모두 U-자형 형상으로 제작되었으며, 압력과 질량 유동 사이의 위상 조절을 위하여 오리피스 밸브와 이중 유입 밸브를 사용하였다. 개발된 맥동관 냉동기의 냉각 성능 목표는 1단(80 K)과 2단(20 K)에서 각각 45 W와 5 W이다. 기초 시험에서는 위상 조절용 밸브들의 개도와 작동 조건에 대한 냉각 특성과 부하 특성 시험을 수행하였다. 특히, 본 연구에서는 로터리 밸브 및 위상 조절 기구의 배치로 인해 고온부 형상이 복잡한 맥동관 냉동기를 크라이오 펌프로의 적용 편의성을 위하여 고온부 외형 구조를 단순화하였으며, 개발된 맥동관 냉동기와 기존에 크라이오 펌프에 적용되는 GM 극저온 냉동기를 비교, 고찰하였다.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.16 no.12
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• pp.2716-2724
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• 2012

In this paper, a Phase Difference-to-Voltage Converter (PDVC) has been introduced into a conventional fractional-N PLL to suppress fractional spurs. The PDVC controls charge pump current depending on the phase difference of two input signals to phase frequency detector. The charge pump current decreases as the phase difference of two input signals increase. It results in the reduction of fractional spurs in the proposed fractional-N PLL. The proposed fractional-N PLL with PDVC has been designed based on a 1.8V $0.18{\mu}m$ CMOS process and proved by HSPICE simulation.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.45 no.7
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• pp.77-80
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• 2008

In this paper, low phase noise VCO using novel compact microstrip spiral resonator is proposed. A spiral resonator has super compact dimension, low insertion losses in the passband and high level of rejection in the stopband with sharp cutoff and a large coupling coefficient value, which makes a high Q value, and has reduced the phase noise. To increase the tuning range of VCO, varactor diode has been connected at the tunable negative resistance in VCO. This VCO has presented the oscillation frequency of $5.686{\sim}5.841GHz$, harmonics -29.83 dBc and phase noise of $-115.16{\sim}-115.17dBc/Hz$ at the offset frequency of 100 KHz.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.17 no.12 s.115
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• pp.1143-1149
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• 2006

The microstrip square open loop resonator has been employed to reduce the phase noise in VCO. The microstrip square open loop resonator has the large coupling coefficient value, which makes a high Q value, and has reduced the phase noise of VCO. To increase the tuning range of VCO, varactor diode has been connected at the tunable negative resistance in VCO. The output power and harmonic characteristics of VCO has been obtained 4.83 dBm and -28.83 dBc, respectively. The phase noise of VCO has been $-112.33{\sim}-116.16dBc/Hz$ @ 100 kHz in the tuning range, $5.735{\sim}5.845GHz$.

• Proceedings of the Optical Society of Korea Conference
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• 2000.02a
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• pp.306-307
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• 2000

1962년 Armstrong 등에 의해 second harmonic generation(SHG) 의 이론이 완성된 후 SHG 효율을 높이기 위한 방법으로 비선형성이 큰 물질의 개발과 더불어 위상정합(phase matching)을 만족시키는 여러가지 방법이 연구 되었다. 특히 위상정합의 경우 지금까지는 복굴절을 이용하는 방법이 널리 사용되었으나 이 경우 입사광의 파장이 제한적이고, 많은 무기물 결정에서 비선형광학계수의 가장 큰 텐서 성분인 $d_{zzz}$를 사용할 수 없다는 단점을 가지고 있다. 반면 유사위상정합(Quasi-phase matching:QPM) 은 비선형광학계수( $d_{zzz}$)의 방향을 결맞음 길이(coherence length)마다 분극반전 시켜주어 2차 조화파의 진폭을 길이방향으로 계속 증가시키는 방법으로 구역반전된 길이를 조절하면 거의 모든 파장에 대해 비임계 위상정합( $d_{zzz}$ 사용)이 가능하고, 2차 조화파가 기본파의 전파경로에서 벗어나는 walk-off 현상이 없어 SHG 전환효율을 극대화할 수 있다. (중략). (중략)

• Transactions of the Korean Society of Automotive Engineers
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• v.2 no.4
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• pp.1-8
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• 1994

이 논문에서 우리는 발전하는 전단층의 2차원 Wave Mode에 대한 비선형 상호작용에 대한 문제를 다루었다. 총 위상각은 Wave Mode ij와 k$\ell$의 상응하는 에너지와 위상 상호작용을 조절한다. 그러므로 이 논문의 목적은 전단층에서 Lange-Scale 구조의 초기 위상각의 효과를 조사하고자 하는 것이다. 이 연구에서 우리는 Subharmonic의 존재는 전단층의 성장에 상당한 영향을 준다는 것을 알았고 Entrainment에서도 증가하는데 영향을 준다는 것을 알았다. 우리는 또한 Mean Flaw와 Fundamental의 다른 초기 위상각의 효과는 Subharmonic이 성장하는 먼 Downstream 영역에서 보여지기 시작한다는 것을 알았다.

• Journal of Biomedical Engineering Research
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• v.20 no.2
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• pp.165-172
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• 1999

An enhancement technique for phase dependent image contrast in MRI(Manetic Resonance Imaging) is proposed. Because the method can enhance inherent phase contrast it is suited for susceptibility imaging and flow imaging where intravoxel phase is a source of image contrast. In this paper, applying external phase in the voxel enhances phase contrast. The external phase is generated by a tailored RF pulse so that one can control the phase contrast and even produces phase only contrast. Signal intensity due to both inherent phase and external phase is analyzed and the proposed technique is applied to a susceptibility effect only imaging and a flow effect only imaging. To verify the proposed technique, computer simulations are performed and their results are given.

• Journal of the Computational Structural Engineering Institute of Korea
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• v.16 no.1
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• pp.59-68
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• 2003

An optimization Program is developed to produce new topologies of plane structures under multiload case. A four-node finite element is used in the response analysis to reduce the computation time and to ultimately achieve practical topology optimization. The bilinear finite element is prone to produce chequer-boarding phenomenon and a simple filtering process is therefore adopted. An artificial material model is employed to represent the structural material and the resizing algorithm based on the optimality criteria is adopted to update the material density parameter during optimization process. With newly developed optimization program, the comparison study has been made between single and multiload cases and its results are described in this paper. From numerical results, it appears that multiload case should be considered to achieve the practical topology optimization.

• The Journal of the Korea Contents Association
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• v.10 no.2
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• pp.72-80
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• 2010

The 1Gbps clock and data recovery (CDR) circuit using the proposed multi-point phase detector (PD) is presented. The proposed phase detector generates up/down signals comparing 3-point that is data transition point and clock rising/falling edge. The conventional PD uses the pulse width modulation (PWM) that controls the voltage controlled oscillator (VCO) using the width of a pulse period's multiple. However, the proposed PD uses the pulse number modulation (PNM) that regulates the VCO with the number of half clock cycle pulse. Therefore the proposed PD can controls VCO preciously and reduces the jitter. The CDR circuit is tested using 1Gbps $2^{31}-1$ pseudo random bit sequence (PRBS) input data. The designed CDR circuit shows that is capable of recovering clock and data at rates of 1Gbps. The recovered clock jitter is 7.36ps at 1GHz and the total power consumption is about 12mW. The proposed circuit is implemented using a 0.18um CMOS process under 1.8V supply.