• Journal of Korea Water Resources Association
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• v.55 no.9
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• pp.687-700
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• 2022

For comprehensively assessment the water resources performance of multi-purpose dams and water supply dams in South Korea, a methodology was proposed to utilize the durational reliability along with the integrated auxiliary indicators including resiliency, dimensionless vulnerability, water resource efficiency, specific inflow, and specific water supply. In addition, for the purpose of sustainable dam operation in the future, a plan to grade the water resources performance was presented to periodically evaluate the performance and determine the priority of each dam's structural or non-structural planning according to the evaluation results. As major results, in the case of Sumjingang Dam, the durational reliability was 99.0%, but the integrated auxiliary index was the lowest of 44 points, which was 5th grade. This means that despite the current high reliability, hydrological changes due to future climate change or regional change of water demand-supply balance can have significant impacts on the water resources performances. In contrast, the Chungju Dam with a durational reliability of 93.0%, which is below the average among all multi-purpose dams, shows the 76 points of the integrated auxiliary index, which is 3^rd highest following the Soyanggang Dam and the Namgang Dam. Nevertheless, due to the size of the basin, the specific inflow is sufficiently high as 185%, so the actual performance could be evaluated relatively high. The water supply dams designed for a single purpose tend to be evaluated relatively high because they have a high proportion of industrial and municipal water supply and have enough room for the supply capacity.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.11 s.353
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• pp.58-68
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• 2006

This work proposes a 10b 250MS/s $1.8mm^2$ 85mW 0.13um CMOS A/D Converter (ADC) for high-performance integrated systems such as next-generation DTV and WLAN simultaneously requiring low voltage, low power, and small area at high speed. The proposed 3-stage pipeline ADC minimizes chip area and power dissipation at the target resolution and sampling rate. The input SHA maintains 10b resolution with either gate-bootstrapped sampling switches or nominal CMOS sampling switches. The SHA and two MDACs based on a conventional 2-stage amplifier employ optimized trans-conductance ratios of two amplifier stages to achieve the required DC gain, bandwidth, and phase margin. The proposed signal insensitive 3-D fully symmetric capacitor layout reduces the device mismatch of two MDACs. The low-noise on-chip current and voltage references can choose optional off-chip voltage references. The prototype ADC is implemented in a 0.13um 1P8M CMOS process. The measured DNL and INL are within 0.24LSB and 0.35LSB while the ADC shows a maximum SNDR of 54dB and 48dB and a maximum SFDR of 67dB and 61dB at 200MS/s and 250MS/s, respectively. The ADC with an active die area of $1.8mm^2$ consumes 85mW at 250MS/s at a 1.2V supply.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.11 s.353
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• pp.48-57
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• 2006

This work describes a 12b 200KHz 0.52mA $0.47mm^2$ algorithmic ADC for sensor applications such as motor controls, 3-phase power controls, and CMOS image sensors simultaneously requiring ultra-low power and small size. The proposed ADC is based on the conventional algorithmic architecture with recycling techniques to optimize sampling rate, resolution, chip area, and power consumption. The input SHA with eight input channels for high integration employs a folded-cascode architecture to achieve a required DC gain and a sufficient phase margin. A signal insensitive 3-D fully symmetrical layout with critical signal lines shielded reduces the capacitor and device mismatch of the MDAC. The improved switched bias power-reduction techniques reduce the power consumption of analog amplifiers. Current and voltage references are integrated on the chip with optional off-chip voltage references for low glitch noise. The employed down-sampling clock signal selects the sampling rate of 200KS/s or 10KS/s with a reduced power depending on applications. The prototype ADC in a 0.18um n-well 1P6M CMOS technology demonstrates the measured DNL and INL within 0.76LSB and 2.47LSB. The ADC shows a maximum SNDR and SFDR of 55dB and 70dB at all sampling frequencies up to 200KS/s, respectively. The active die area is $0.47mm^2$ and the chip consumes 0.94mW at 200KS/s and 0.63mW at 10KS/s at a 1.8V supply.