• The Journal of the Korea institute of electronic communication sciences
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• v.14 no.2
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• pp.309-316
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• 2019

In this paper, a low-jitter delay-locked loop that compensates for local clock skew is presented. The proposed DLL consists of a phase splitter, a phase detector(PD), a charge pump, a bias generator, a voltage-controlled delay line(VCDL), and a level converter. The VCDL uses self-biased delay cells using current mode logic(CML) to have insensitive characteristics to temperature and supply noises. The phase splitter generates two reference clocks which are used as the differential inputs of the VCDL. The PD uses the only single clock from the phase splitter because the PD in the proposed circuit uses CMOS logic that consumes less power compared to CML. Therefore, the output of the VCDL is also converted to the rail-to-rail signal by the level converter for the PD as well as the local clock distribution circuit. The proposed circuit has been designed with a $0.13-{\mu}m$ CMOS process. A global CLK with a frequency of 1-GHz is externally applied to the circuit. As a result, after about 19 cycles, the proposed DLL is locked at a point that the control voltage is 597.83mV with the jitter of 1.05ps.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.19 no.9
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• pp.1028-1036
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• 2008

In the OFDM system, IQ imbalance problem happens at the RF front-end of transceiver, which degrades the BER(bit error rate) performance because it affects the constellation in the received signal. Also, phase noise is generated in the local oscillator of transceivers and it destroys the orthogonality between the subcarriers. Conventional PNS algorithm is effective for phase noise suppression, but it is not useful anymore when there are jointly IQ(In-phase and Quadrature) imbalance and phase noise. Therefore, in this paper, we analyze the effect of IQ imbalance and phase noise generated in the down-conversion of the receiver. Then, we estimate and compensate the IQ imbalance and phase noise at the same time. Compared with the conventional method that IQ imbalance after IFFT is estimated and compensated in front of FFT via the feedback, this proposed method extracts and compensates effect of IQ imbalance after FFT stage. In case IQ imbalance and phase noise exist at the same time, we can decrease complexity because it is needless to use elimination of IQ imbalance in time domain and training sequences and preambles. Also, this method shows that it reduces the ICI and CPE component using adaptive forgetting factor of MMSE after FFT.

• Bulletin of the Korean Space Science Society
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• 2003.10a
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• pp.30-30
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• 2003

GPS와 VLBI와 같은 우주측지 기술을 이용한 정밀 측위는 수 mn 정밀도의 관측소 좌표결정과 1 mm/year 정도의 고정밀 속도결정에 이용된다. 이를 위해서는 여러 가지 오차 요인들과 다양한 물리적 현상에 대한 모델링이 이루어져야 한다. 그 중의 하나가 해수 하중(ocean loading)에 의한 수직방향의 지각변위이다. 특히 한반도의 서해안은 복잡한 리아스식 해안으로 이루어져 있고, 조수간만의 차이가 크기 때문에 현존하는 모델의 정확도가 떨어진다. KVN(Korean VLBI Network)사업에서 추진하는 3기의 VLBI 중 2기가 서울과 제주도에 설치될 계획이므로, 해수하중에 의한 지각변위에 관한 연구가 선행되어야 한다. 또한 국내 GPS상시관측소의 많은 수가 서해안 지역에 설치되어 있다. 본 연구에서는 서해안 지역의 해수하중에 의한 수직방향의 지각변위를 GPS로 관측하고 이를 서해안 해수조류 모델의 정밀도를 향상시키는데 필요한 기초연구를 수행하였다. 서해안의 4개 GPS 관측소 위치에서의 해수하중에 의한 지각변위를 계산해본 결과 인천 지역에는 3 cm에 육박하는 지각변위가 수직으로 발생함을 알 수 있었다. 같은 크기와 위상의 지각변위 진폭을 GPS로 검출하기 위한 여러 가지 오차 보정과 GIPSY를 이용한 고정밀 키네마틱 GPS 자료처리에 대하여 상세히 소개한다.

• Proceedings of the KIEE Conference
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• 2000.07a
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• pp.40-42
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• 2000

동일한 변압기에서 인출된 서로 다른 선로 중 한 곳에서 지락이나 단락등의 사고가 발생하면, 고장선로 뿐 아니라 주변선로에도 사고가 제거되기 전까지 전압강하 현상이 발생하게 된다. 근래에 들어서 이러한 현상에 의한 피해사례가 많이 보고되고 있으며, 전력공급자나 수용가에서도 이 문제에 대해 높은 관심을 보이고 있다. 본 논문에서는 이러한 문제에 대한 대책으로 직렬변압기를 통하여 전압을 주입함으로서 부하에 항상 안정적인 전압을 공급할 수 있는 순간전압 보상장치에 대하여 연구하였다. 본 논문에서는 입력 전압의 peak값을 검출하여 직렬 주입될 전압의 크기와 위상을 구하는 방식을 사용하였고, 20kW급 prototype을 제작하여 실험을 수행하였다.

• Proceedings of the KIPE Conference
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• 2017.07a
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• pp.469-470
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• 2017

디지털 계측기는 전압 또는 전류 한주기에 대하여 여러 번 샘플링 하여 실효치를 구하고 위상은 전압영점에서 카운터를 시작하여 전류 영점에서 그 카운터의 값에 의해 전력을 구하는 것이 일반적이다. 그러나 계측대상 주파수가 샘플링 주파수와 유사한 경우 사실상 전력 계측이 불가능하게 되는 취약점을 안고 있다. 따라서 본 논문에서는 계측대상 주파수가 샘플링 주파수와 유사한 경우 샘플링 시프트 기능을 사용하여 계측하는 정규화 기법과 이를 이용하여 DFT를 사용하여 각 차수의 고조파 성분을 분석할 수 있는 알고리즘을 제안한다. 또한 제안된 방식을 Psim을 이용한 시뮬레이션을 통하여 그 타당성을 검증하였다.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.4
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• pp.36-42
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• 2008

40Gb/s CMOS Clock and Data Recovery circuit design for optical serial link is proposed. The circuit generates 8 multiphase clock using LC tank PLL and controls the phase between the clock and the data using the $2{\times}$ oversampling Bang-Bang PD. 40Gb/s input data is 1:4 demultiplexed and recovered to 4 channel 10Gb/s outputs. The design was progressed to separate the analog power and the digital power. The area of the chip is $2.8{\times}2.4mm^2$ for the inductors and the power dissipation is about 200mW. The chip has been fabricated using 0.18um CMOS process. The measured results show that the chip recovers the data up to 9.5Gb/s per channel(Equivalent to serial input rate of up to 38Gb/s).

• Journal of the Institute of Convergence Signal Processing
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• v.15 no.4
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• pp.169-175
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• 2014

NG-SDH system is connected with networks throughout optical fibers. Network synchronization controller is a necessary for the data synchronization in each optical transmission system. In this paper, we have design and implementation the network synchronization controller using SOPC(system on a programmable chip) design technic. For this network synchronization controller we use FPGA in Altera. FPGA includes 32bit CPU, DPRAM(dual port ram), digital input/output port, transmitter and receiver framer, phase difference detector. We also confirm that designed network synchronization controller satisfies the ITU-T G.813 timing requirements.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.2
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• pp.19-24
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• 2007

With recent advancement of high-speed, multi-gigabit data transmission capabilities, serial links have been more widely adopted in industry than parallel links. Since the parallel link design forces its transmitter to transmit both the data and the clock to the receiver at the same time, it leads to hardware's intricacy during high-speed data transmission, large power consumption, and high cost. Meanwhile, the serial links allows the transmitter to transmit data only with no synchronized clock information. For the purpose, clock and data recovery circuit becomes a very crucial key block. In this paper, a 5.4Gbps half-rate bang-bang CDR is designed for the applications of high-speed graphic DRAM interface. The CDR consists of a half-rate bang-bang phase detector, a current-mirror charge-pump, a 2nd-order loop filter, and a 4-stage differential ring-type VCO. The PD automatically retimes and demultiplexes the data, generating two 2.7Gb/s sequences. The proposed circuit is realized in 66㎚ CMOS process. With input pseudo-random bit sequences (PRBS) of $2^{13}-1$, the post-layout simulations show 10psRMS clock jitter and $40ps_{p-p}$ retimed data jitter characteristics, and also the power dissipation of 80mW from a single 1.8V supply.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.25 no.6
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• pp.671-678
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• 2014

This paper presents a Ka-band FMCW sensor that has high linearity by improving a nonlinear behavior of the voltage controlled oscillator. Due to the nonlinear characteristics of the voltage controlled oscillator for the conventional method, the drift of beat frequency can cause inaccuracy and errors to the extracted results. A Ka-band FMCW signal with fast transition time could be generated by using both direct digital synthesizer and phase locked loop in this research. The implemented FMCW sensor showed very high accuracy in beat frequency through the test.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.25 no.1B
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• pp.183-192
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• 2000

In this paper, the dual looped CMOS PLL with 3-250MHz input locking range at a single 13.3V is designed. This paper proposed a new PLL architecture with a current pumping algorithm to improve voltage-to-frequencylinearity of VCO(Voltage Controlled Oscillator). The designed VCO operates at a wide frequency range of75.8MHz-lGHz with a high linearity. Also, PFD(Phase frequency Detector) circuit preventing voltage fluctuation of the charge pump with loop filter circuit under the locked condition is designed. The simulation results of the PLL using 0.6 um N-well single poly triple metal CMOS technology illustrate a locking time of 3.5 us, a power dissipation of 92mW at 1GHz operating frequency with 125MHz of input frequency. Measured results show that the phase noise of VCO with V-I converter is -100.3dBc/Hz at a 100kHz offset frequency.