• Title/Summary/Keyword: 웨이퍼 표면

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Plasma Uniformity Numerical Modeling of Geometrical Structure for 450 mm Wafer Process System (450 mm 웨이퍼 공정용 System의 기하학적 구조에 따른 플라즈마 균일도 모델링 분석)

  • Yang, Won-Kyun;Joo, Jung-Hoon
    • Journal of the Korean Vacuum Society
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    • v.19 no.3
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    • pp.190-198
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    • 2010
  • Asymmetric model for plasma uniformity by Ar and $CF_4$ was modeled by the antenna structure, the diameter of chamber, and the distance between source and substrate for the development of plasma equipment for 450 mm wafer. The aspect ratio of chamber was divided by diameter, distance from substrate, and pumping port area. And we found the condition with the optimized plasma uniformity by changing the antenna structure. The drift diffusion and quasi-neutrality for simplification were used, and the ion energy function was activated for the surface recombination and etching reaction. The uniformity of plasma density on substrate surface was improved by being far of the distance between substrate wall and chamber wall, and substrate and plasma source. And when the antenna of only 2 turns was used, the plasma uniformity can improve from 20~30% to 4.7%.

A Study on Solar Cell Wafer Cleaning using Ozonate Water (오존수를 이용한 태양전지용 웨이퍼의 세정에 관한 연구)

  • Moon, Se-Ho;Chai, Sang-Hoon;Son, Young Su
    • Journal of the Institute of Electronics and Information Engineers
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    • v.50 no.11
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    • pp.43-49
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    • 2013
  • We have studied on ozonate water cleaning mechanisms to apply in manufacturing process of 156 mm silicon wafer which is used in the solar cell fabrication. We have analyzed contamination sources on wafer surface which causes poor quality and performance of products in fabrication process, and examined cleaning process using ozonate water to eliminate it. Using this novel technology particles are removed over 94%, and remained organic materials are removed more over 45%.

Flexible Module Packaging using MEMS technology (MEMS 기술을 이용한 Flexible Module Packaging)

  • 황은수;최석문;주병권
    • Proceedings of the International Microelectronics And Packaging Society Conference
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    • 2002.05a
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    • pp.74-78
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    • 2002
  • MEMS공정을 이용하여 폴리실리콘의 piezoresistivity를 이용한 스트레인 센서어레이를 제작하였고, 이 센서 어레이를 flexible substrate에 패키징하는 공정을 개발하였다. 실리콘 웨이퍼에 표면 가공(surface micromachining)된 센서는 폴리이미드 코팅, release-etch 방법을 통해 웨이퍼로부터 분리되어 폴리이미드를 기판으로 하는 flexible sensor array module을 완성할 수 있었다. 공정은 희생층과 절연층을 증착하고 폴리실리콘 0.5 $\mu\textrm{m}$을 증착, 도핑 및 패터닝하여 센서 어레이를 구성하였다. 이 센서어레이를 flexible substrate에 패키징 하기 위해서 폴리이미드를 코팅하여 15 $\mu\textrm{m}$의 막을 구성하였고, 100% $O_2$RIE를 이용한 선택적 식각 방법으로 via hole을 구성하였다. 이후 전기도금을 통해 회로를 구성하여 1단계 패키징(die to chip carrier)과 2단계 패키징(chip to substrate)을 웨이퍼 레벨에서 완성하였다. 희생층을 제거함으로서 웨이퍼로부터 센서어레이 모듈을 분리하였다. 제작되어진 센서 모듈은 임의의 곡면에 실장이 가능하도록 충분한 flexibility를 얻을 수 있었다.

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SOI wafer formation by ion-cut process and its characterization (Ion-cut에 의한 SOI웨이퍼 제조 및 특성조사)

  • Woo H-J;Choi H-W;Bae Y-H;Choi W-B
    • Journal of the Korean Vacuum Society
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    • v.14 no.2
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    • pp.91-96
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    • 2005
  • The silicon-on-insulator (SOI) wafer fabrication technique has been developed by using ion-cut process, based on proton implantation and wafer bonding techniques. It has been shown by SRIM simulation that 65keV proton implantation is required for a SOI wafer (200nm SOI, 400nm BOX) fabrication. In order to investigate the optimum proton dose and primary annealing condition for wafer splitting, the surface morphologic change has been observed such as blistering and flaking. As a result, effective dose is found to be in the $6\~9\times10^{16}\;H^+/cm^2$ range, and the annealing at $550^{\circ}C$ for 30 minutes is expected to be optimum for wafer splitting. Direct wafer bonding is performed by joining two wafers together after creating hydrophilic surfaces by a modified RCA cleaning, and IR inspection is followed to ensure a void free bonding. The wafer splitting was accomplished by annealing at the predetermined optimum condition, and high temperature annealing was then performed at $1,100^{\circ}C$ for 60 minutes to stabilize the bonding interface. TEM observation revealed no detectable defect at the SOI structure, and the interface trap charge density at the upper interface of the BOX was measured to be low enough to keep 'thermal' quality.

Estimating High-Frequency Damping of a Beam through Electro-Mechanical Signatures of Piezoelectric Wafer Mounted on the Beam (보에 부착된 압전웨이퍼의 전기역학적 신호를 통한 고주파수 대역 감쇠 추정)

  • Shin, Yong Jae;Park, Hyun Woo
    • KSCE Journal of Civil and Environmental Engineering Research
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    • v.37 no.1
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    • pp.217-229
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    • 2017
  • The high-frequency electro-mechanical signatures, which are excited and received by piezoelectric wafers mounted on a beam, are sensitive to incipient defect in a beam. Predicting the sensing range of the piezoelectric wafers is needed to effectively conduct damage assessment of a beam through utilizing their advantage. Damping of a beam plays the most important role in determining the sensing range among other features. This paper has proposed a scheme for estimating high-frequency damping of a beam through electro-mechanical signatures of piezoelectric wafers mounted on the beam. Considering damping effect while resonance of a beam evolves, wave perspective is adopted to formulate the electro-mechanical signatures of piezoelectric wafers. The damping of a beam is estimated through the least squares method minimizing the difference between the calculated and the measured damping ratio function values which are obtained from formulated and measured electro-mechanical signatures, respectively. The validity of the proposed scheme has been demonstrated through numerical and experimental examples using an aluminum beam with collocated piezoelectric wafers.

AG(Anti-glare)를 이용한 태양전지 특성 분석

  • Jeong, Sang-Hun;Jo, Yeong-U;Lee, Yun-Ho;Gong, Dae-Yeong;Seo, Chang-Taek;Jo, Chan-Seop;Lee, Jong-Hyeon
    • Proceedings of the Korean Vacuum Society Conference
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    • 2010.02a
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    • pp.286-286
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    • 2010
  • 최근에 환경 오염과 화석 에너지의 고갈 문제를 해결하기 위하여 태양광을 전기 에너지로 변환하는 태양전지 연구에서 가장 이슈가 되는 부분은 저가격화와 고효율이다. 상용화 되어 있는 대부분의 태양전지는 단결정 실리콘 웨이퍼와 다결정 실리콘 웨이퍼를 사용한다. 실리콘 웨이퍼의 원자재 가격을 낮추는 방법에는 한계가 있기 때문에 태양전지 제작 공정에서 공정 단가를 낮추는 방법이 많이 연구되고 있고, 실리콘 웨이퍼가 가지는 재료의 특성상 화합물을 이용한 태양전지 보다 낮은 효율을 가질 수밖에 없기 때문에 반도체 소자 공정을 응용하여 실리콘 웨이퍼 기판에서 고효율을 얻는 방법으로 연구가 진행 되고 있다. 본 연구에서는 마이크로 블라스터를 이용하여 태양전지 cell 상부에 AG(anti-glare)를 가지는 유리 기판을 형성하여 낮은 단가로 태양전지 cell의 효율을 향상시키기 위한 연구를 진행 하였다. 태양전지 cell 상부에 AG를 가지는 유리 기판을 형성하게 되면 태양의 위도가 낮아 표면에서 대부분 반사되는 태양광을 태양전지 cell에서 광기전력효과가 일어나게 하여 효율을 향상시킨다. 이때 사용한 micro blaster 공정은 고속의 입자가 재료를 타격할 때 입자의 아래에는 고압축응력이 발생하게 되고, 이 고압 축응력에 의하여 소성변형과 탄성변형이 발생된다. 이러한 변형이 발전되어 재료의 파괴 초기값보다 크게 되면 크랙이 발생되고, 점점 더 발전하게 되면 재료의 제거가 일어나는 단계로 이루어지는 기계적 건식 식각 공정 기술이라 할 수 있다. 먼저 유리 기판에 마이크로 블라스터 장비를 이용하여 AG를 형성한다. AG는 $Al_2O_3$ 파우더의 입자 크기, 분사 압력, 노즐과 기판과의 간격, 반복 횟수, 노즐 이동 속도 등의 공정 조건에 따른 유리 기판 표면에서의 광학적 특성 및 구조적 특성에 관하여 분석하였다. 일반적인 태양전지 cell 제작 공정에 따라 cell을 제작 한후 AG 유리 기판을 상부에 형성시키고 솔라시뮬레이터를 이용하여 효율을 측정하였다. 이때 솔라시뮬레이터의 광원이 고정되어 있기 때문에 태양전지 cell에 기울기를 주어 태양의 위도 변화에 대해 간접적으로 측정하였다. AG 유리 기판이 태양전지 cell 상부에 형성 되었을 때와 없을 때를 각각 비교하여 AG 유리 기판이 형성된 태양전지 cell에서의 효율 향상을 확인하였다.

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Formation of lotus surface structure for high efficiency silicon solar cell (고효율 실리콘 태양전지를 위한 lotus surface 구조의 형성)

  • Jung, Hyun-Chul;Paek, Yeong-Kyeun;Kim, Hyo-Han;Eum, Jung-Hyun;Choi, Kyoon;Kim, Hyung-Tae;Chang, Hyo-Sik
    • Journal of the Korean Crystal Growth and Crystal Technology
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    • v.20 no.1
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    • pp.7-11
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    • 2010
  • The reduction of optical losses in mono-crystalline silicon solar cell by surface texturing is a critical step to improve the overall cell efficiency. In this study, we have changed the sub-micrometer structure on the micrometer pyramidal structure by 2-step texturing. The Ag particles were coated on the micrometer pyramid surface in $AgNO_3$ solution, and then the etching with hydrogen fluoride and hydrogen peroxide created even smaller nano-pyramids in these pyramids. As a result, we observed that the changes of size and thickness of nano structure on pyramidal surface were determined by $AgNO_3$ concentration and etching time. Using 2-step texturing, the surface of wafers is etched to resemble the rough surface of a lotus leaf. Lotus surface can reduce average reflectance from 10% to below 3%. This reflectance is less than conventional textured wafer including anti-reflection coating.

A Study on the Release Characteristics During Wafer-Level Lens Molding Using Thermosetting Materials (열경화성 소재를 사용한 웨이퍼 레벨 렌즈 성형 중 이형 특성에 관한 연구)

  • Park, Si-Hwan;Hwang, Yeon;Kim, Dai-Geun
    • Journal of the Korea Academia-Industrial cooperation Society
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    • v.22 no.1
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    • pp.461-467
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    • 2021
  • Among the defect factors that can occur when a wafer-level lens is molded using a thermosetting material, the mold sticking problem of a molded lens during the release process can damage the molded substrate and deform the substrate at the wafer level. An experiment was conducted to examine the factors affecting the demolding force in the lens forming process. The demolding force was examined according to the coating material of the molds. The mold was surface-treated with ITO and Ti, followed by plasma treatment in an O2 atmosphere. A DLC coating was then performed, and the curing and releasability were examined. A coating method for the pull-off experiment was selected based on the results. To measure the demolding force according to the curing process conditions, a method of curing at a constant pressure and a method of curing at a constant position were applied. As a result, the TiO2 surface treatment reduced the release force. When cured by controlling the location, curing shrinkage can reduce the adhesion energy of the interface during curing, resulting in better demolding.