• Proceedings of the Korean Vacuum Society Conference
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• 2010.02a
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• pp.456-456
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• 2010

CMOS 소자가 서브마이크론($0.1\;{\mu}m$) 이하로 스케일다운 되면서 단채널 효과(short channel effect), 게이트 산화막(gate oxide)의 누설전류(leakage current)의 증가와 높은 직렬저항(series resistance) 등의 문제가 발생한다. CMOS 소자의 구동전류(drive current)를 높이고, 단채널 효과를 줄이기 위한 가장 효율적인 방법은 소스 및 드레인의 얕은 접합(shallow junction) 형성과 직렬 저항을 줄이는 것이다. 플라즈마 도핑 방법은 플라즈마 밀도 컨트롤, 주입 바이어스 전압 조절 등을 통해 저 에너지 이온주입법보다 기판 손상 및 표면 결함의 생성을 억제하면서 고농도로 얕은 접합을 형성할 수 있다. 그리고 얕은 접합을 형성하기 위해 주입된 불순물의 활성화와 확산을 위해 후속 열처리 공정은 높은 온도에서 짧은 시간 열처리하여 불순물 물질의 활성화를 높여주면서 열처리로 인한 접합 깊이를 얕게 해야 한다. 그러나 접합의 깊이가 줄어듦에 따라서 소스 및 드레인의 표면 저항(sheet resistance)과 접촉저항(contact resistance)이 급격하게 증가하는 문제점이 있다. 이러한 표면저항과 접촉저항을 줄이기 위한 방안으로 실리사이드 박막(silicide thin film)을 형성하는 방법이 사용되고 있다. 본 논문에서는 (100) p-type 웨이퍼 He(90 %) 가스로 희석된 $PH_3$(10 %) 가스를 사용하여 플라즈마 도핑을 실시하였다. 10 mTorr의 압력에서 200 W RF 파워를 인가하여 플라즈마를 생성하였고 도핑은 바이어스 전압 -1 kV에서 60 초 동안 실시하였다. 얕은 접합을 형성하기 위한 불순물의 활성화는 ArF(193 nm) excimer laser를 통해 $460\;mJ/cm^2$의 에니지로 열처리를 실시하였다. 그리고 낮은 접촉비저항과 표면저항을 얻기 위해 metal sputter를 통해 TiN/Ti를 $800/400\;{\AA}$ 증착하고 metal RTP를 사용하여 실리사이드 형성 온도를 $650{\sim}800^{\circ}C$까지 60 초 동안 열처리를 실시하여 $TiSi_2$ 박막을 형성하였다. 그리고 $TiSi_2$의 두께를 측정하기 위해 TEM(Transmission Electron Microscopy)을 측정하였다. 화학적 결합상태를 분석하기 위해 XPS(X-ray photoelectronic)와 XRD(X-ray diffraction)를 측정하였다. 접촉비저항, 접촉저항과 표면저항을 분석하기 위해 TLM(Transfer Length Method) 패턴을 제작하여 I-V 특성을 측정하였다. TEM 측정결과 $TiSi_2$의 두께는 약 $580{\AA}$ 정도이고 morphology는 안정적이고 실리사이드 집괴 현상은 발견되지 않았다. XPS와 XRD 분석결과 실리사이드 형성 온도가 $700^{\circ}C$에서 C54 형태의 $TiSi_2$ 박막이 형성되었고 가장 낮은 접촉비저항과 접촉저항 값을 가진다.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.20 no.6
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• pp.80-85
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• 2019

Vanadium dioxide is a well-known metal-insulator phase transition material. Lots of researches of vanadium redox flow batteries have been researched as large scale energy storage system. In this study, vanadium oxide($VO_x$) thin films were applied to cathode for lithium ion battery. The $VO_x$ thin films were deposited on Si substrate($SiO_2$ layer of 300 nm thickness was formed on Si wafer via thermal oxidation process), quartz substrate by RF magnetron sputter system for 60 minutes at $500^{\circ}C$ with different RF powers. The surface morphology of as-deposited $VO_x$ thin films was characterized by field-emission scanning electron microscopy. The crystallographic property was confirmed by Raman spectroscopy. The optical properties were characterized by UV-visible spectrophotometer. The coin cell lithium-ion battery of CR2032 was fabricated with cathode material of $VO_x$ thin films on Cu foil. Electrochemical property of the coin cell was investigated by electrochemical analyzer. As the results, as increased of RF power, grain size of as-deposited $VO_x$ thin films was increased. As-deposited thin films exhibit $VO_2$ phase with RF power of 200 W above. The transmittance of as-deposited $VO_x$ films exhibits different values for different crystalline phase. The cyclic performance of $VO_x$ films exhibits higher values for large surface area and mixed crystalline phase.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.12 no.4
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• pp.366-372
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• 2019

In this paper, we fabricated a capacitive humidity sensor with an IDT(Interdigitated) electrode using commercial polyimide containing fluorine, and its properties were measured and analyzed. First, in order to analyze the composition of commercial polyimide, EDS analysis was performed after patterning process on a silicon wafer. The area of the humidity sensor was $1.56{\times}1.66mm^2$, and the width of the electrode and the gap between the electrodes were $3{\mu}m$ each. The number of electrodes was 166 and the length of the electrode was 1.294mm for the sensitivity of the sensor. The fabricated sensor showed that the sensitivity was 24 fF/%RH, linearity <${\pm}2.5%RH$ and hysteresis <${\pm}4%RH$. As a result of measuring the capacitance value according to the frequency change, the capacitance vlaue decreased with increasing frequency. Capacitance deviations with 10kHz and 100kHz were measured as 0.3pF on average.

• Journal of Adhesion and Interface
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• v.22 no.2
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• pp.57-62
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• 2021

Recently, the atomically thin two-dimensional transition-metal dichalcogenides (TMDs) have received considerable attention for the application to next-generation semiconducting devices, owing to their remarkable properties including high carrier mobility. However, while a technique for growing graphene is well matured enough to achieve a wafer-scale single crystalline monolayer film, the large-area growth of high quality TMD monolayer is still a challenging issue for industrial application. In order to enlarge the size of single crystalline MoS₂ monolayer, here, we systematically investigated the effect of process parameters in molten-salt-assisted chemical vapor deposition method. As a result, with optimized process parameters, we found that single crystalline monolayer MoS₂ can be grown as large as 420 ㎛.

• Journal of the Microelectronics and Packaging Society
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• v.28 no.3
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• pp.9-15
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• 2021

Miniaturization of semiconductor devices has recently faced a physical limitation. To overcome this, 3D packaging in which semiconductor devices are vertically stacked has been actively developed. 3D packaging requires three unit processes of TSV, wafer grinding, and bonding, and among these, copper bonding is becoming very important for high performance and fine-pitch in 3D packaging. In this study, the effects of Ti nanolayer on the antioxidation of copper surface and low-temperature Cu bonding was investigated. The diffusion rate of Ti into Cu is faster than Cu into Ti in the temperature ranging from room temperature to 200℃, which shows that the titanium nanolayer can be effective for low-temperature copper bonding. The 12nm-thick titanium layer was uniformly deposited on the copper surface, and the surface roughness (R_q) was lowered from 4.1 nm to 3.2 nm. Cu bonding using Ti nanolayer was carried out at 200℃ for 1 hour, and then annealing at the same temperature and time. The average shear strength measured after bonding was 13.2 MPa.

• Journal of the Microelectronics and Packaging Society
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• v.29 no.1
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• pp.49-54
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• 2022

The copper plating process used to fabricate the submicron damascene pattern of Cu wiring for Si wafer was applied to the plating of a PCB pattern of several tens of microns in size using the same organic additives and current density conditions. In this case, the non-uniformity of the plating thickness inside the pattern was observed. In order to quantitatively analyze the cause, a numerical calculation considering the solution flow and electric field was carried out. The calculation confirmed that the depletion of Cu²⁺ ions in the solution occurred relatively earlier at the bottom corner than the upper part of the pattern due to the plating of the sidewall and the bottom at the corner of the pattern bottom. The diffusion coefficient of Cu²⁺ ions is 2.65 10^-10 m²/s, which means that Cu²⁺ ions move at 16.3 ㎛ per second on average. In the cases of small damascene patterns, the velocity of Cu²⁺ ions is high enough to supply sufficient ions to the inside of the patterns, while sufficient time is required to replenish the exhausted copper ions in the case of a PCB pattern having a size of several tens of microns. Therefore, it is found that the thickness uniformity can be improved by reducing the current density to supply sufficient copper ions to the target area.

• Journal of IKEEE
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• v.26 no.3
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• pp.422-429
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• 2022

A light sensor chip requires a small capacity eFuse (electrical fuse) OTP (One-Time Programmable) memory IP (Intellectual Property) to trim analog circuits or set initial values of digital registers. In this paper, 128-bit eFuse OTP IP is designed using only 3.3V MV (Medium Voltage) devices without using 1.8V LV (Low-Voltage) logic devices. The eFuse OTP IP designed with 3.3V single MOS devices can reduce a total process cost of three masks which are the gate oxide mask of a 1.8V LV device and the LDD implant masks of NMOS and PMOS. And since the 1.8V voltage regulator circuit is not required, the size of the illuminance sensor chip can be reduced. In addition, in order to reduce the number of package pins of the illumination sensor chip, the VPGM voltage, which is a program voltage, is applied through the VPGM pad during wafer test, and the VDD voltage is applied through the PMOS power switching circuit after packaging, so that the number of package pins can be reduced.

• Journal of the Korean Crystal Growth and Crystal Technology
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• v.34 no.1
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• pp.8-15
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• 2024

The CaF₂ single crystal has notable characteristics such as a large band gap (12 eV), excellent transparency over a wide wavelength range, low refractive index and dispersion. Due to these outstanding properties, CaF₂ single crystal has considered as a promising material for short-wavelength light sources in recent lithography processes. However, there is an inherent birefringence of the material at 157 nm and the resulting aberration can be compensated for through the combination of the (100) plane and the (111) plane. Therefore, it is necessary to investigate the characteristics according to the plane. In this study, we analyzed crystallinity, optical properties of commercial CaF₂ single crystal wafers grown by the Czochralski method. In particular, through chemical etching under various conditions, it was confirmed that the shape of etch pits appears differently depending on the plane and the shape and array of specific etch pits affected by dislocations and defects were examined.

• Korean Journal of Materials Research
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• v.6 no.7
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• pp.700-708
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• 1996

Electroless plating technique was utilized to flip chip bonding to improve surface mount characteristics. Each step of plating procedure was studied in terms pf pH, plating temperature and plating time. Al patterned 4 inch Si wafers were used as substrstes and zincate was used as an activation solution. Heat treatment was carried out for all the specimens in the temperature range from room temperature to $400^{\circ}C$ for $30^{\circ}C$ minutes in a vacuum furnace. Homogeneous distribution of Zn particles of size was obtained by the zincate treatment with pH 13 ~ 13.5, solution concentration of 15 ~ 25% at room temperature. The plating rates for both Ni-P and Au electroless plating steps increased with increasing the plating temperature and pH. The main crystallization planes of the plated Au were found to be (111) a pH 7 and (200) and (111) at pH 9 independent of the annealing temperature.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.33A no.2
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• pp.96-113
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• 1996

It has been found that the misfit dislocations in heavily boron-doped layers originate from wafer edges. Moreover, the propagation of the misfit dislocation into a heavily boron-doped region can be suppressed by placing a surrounding undoped region. Using a surrounding undoped region the disloction-free heavily boron-deoped silicon membranes have been fabricated. The measured surface roughness, fracture strength, and residual tensile stress of the membrane are 20.angs. peak-to-peak, 1.39${\times}$10$^{10}$ and 2.7${\times}$10$^{9}$dyn/cm$^{2}$, while those of the conventional heavily boron-doped silicon membrane with high density of misfit dislocations are 500 peak-to-peak, 8.27${\times}$10$^{9}$ and 9.3${\times}$10$^{8}$dyn/cm$^{2}$ respectively. The differences between these two membranes are due to the misfit dislocations. Young's modulus has been extracted as 1.45${\times}$10$^{12}$dyn/cm$^{2}$ for both membranes. Also, the effective lattice constant of heavily boron-doped silicon, the in-plane lattice constant of the conventional membrane, and the density of misfit dislocation contained in the conventional membrane have been extracted as density of misfit dislocation contained in the conventional membrane have been extracted as density of misfit dislocation contained in the conventional membrane have been extracted as 5.424.angs. 5.426.angs. and 2.3${\times}$10$^{4}$/cm for the average boron concentration of 1.3${\times}$10$^{20}$/cm$^{-23}$ cm$^{3}$/atom. Without any buffer layers, a disloction-free lightly boron-doped epitaxial layer with good crsytalline quality has been directly grown on the dislocation-free heavily boron-doped silicon layer. X-ray diffraction analysis revealed that the epitaxial silicon has good crystallinity, similar to that grown on lightly doped silicon substrate. The leakage current of the n+/p gated diode fabricated in the epitaxial silicon has been measured to be 0.6nA/cm$^{2}$ at the reverse bias of 5V.