• Journal of Korea Society of Industrial Information Systems
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• v.27 no.4
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• pp.11-18
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• 2022

A physically unclonable function (PUF) is a circuit that generates random numbers by exploiting natural variation. Since it utilizes variations, which cannot be fully controlled, it can be used to generate true random numbers, but environment change may distort the output. In this paper, we propose a PUF with a confidence signal. We designed a PUF that exploits the difference of the time constant of the circuit and verified that different PUFs generate distinct outputs and the same PUF keeps generating similar outputs regardless of the temperature change. Compared to the existing technique, which employs an error correction code, the proposed technique offers the same level of reliability at the 700 times smaller overhead.

• The Transactions of the Korea Information Processing Society
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• v.7 no.7
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• pp.2149-2160
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• 2000

Recently many efforts on the development of automatic processing system for delivery sequence sorting have been performed in ETRI, which requires the use of postal4-state bar code system to encode delivery points. The 4-state bar code called postal 4-state barcode for high speed processing that has been specifically designed for information processing of logistics and automatic processing of he mail items. The Information of 4-state bar code indicates mail data such as post code, delivery sequence number, error correction code worked, customer information, and a unique ID. This appear addresses the issue on he reduction of reading error in postal 4-state raster beam based bar code reader. The raster beam scanning features are the unequally distributed number of spots per each unit, which cause reading errors. We propose a method for reducing the bar code reading error by adjusting measured values of bar code width to its average value over each interval. The test results show that the above method reduces the average reading error rate approximately by 99.88%.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.29 no.1C
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• pp.1-8
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• 2004

This paper proposes a novel algorithm for a low power turbo decoder based on reduction of number of decoding iterations, targeting power-critical mobile communication devices. Previous researches that attempt to reduce number of decoding iterations, such as CRC-aided and LLR methods, either show degraded BER performance in return for reduced complexity or require additional hardware resources for controlling the number of iterations to meet BER performance, respectively. The proposed algorithm can reduce power consumption without degrading the BER performance, and it is achieved with minimal hardware overhead. The proposed algorithm achieves this by comparing consecutive hard decision results using a simple buffer and counter. Simulation results show that the number of decoding iterations can be reduced to about 60% without degrading the BER performance in the proposed decoder, and power consumption can be saved in proportion to the number of decoding iterations.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.40 no.6
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• pp.459-468
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• 2003

This paper proposes a novel low-cost and high-speed Reed-Solomon (RS) decoder based on a new degree computationless modified Euclid´s (DCME) algorithm. This architecture has quite low hardware complexity compared with conventional modified Euclid´s (ME) architectures, since it can remove completely the degree computation and comparison circuits. The architecture employing a systolic away requires only the latency of 2t clock cycles to solve the key equation without initial latency. In addition, the DCME architecture using 3t＋2 basic cells has regularity and scalability since it uses only one processing element. The RS decoder has been synthesized using the 0.25${\mu}{\textrm}{m}$. Faraday CMOS standard cell library and operates at 200MHz and its data rate suppots up to 1.6Gbps. For tile (255, 239, 8) RS code, the gate counts of the DCME architecture and the whole RS decoder excluding FIFO memory are only 21,760 and 42,213, respectively. The proposed RS decoder can reduce the total fate count at least 23% and the total latency at least 10% compared with conventional ME architectures.

• Journal of Digital Convergence
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• v.13 no.2
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• pp.159-175
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• 2015

The two-dimensional QR code has advantages such as directional nature, enough data storage capacity, ability of error correction, and ability of data restoration. There are two major issues like speed and correctiveness of recognition in the two-dimensional QR code. Therefore, this paper proposes a morphology-based algorithm of detecting the interest region of a barcode. Our research contents can be summarized as follows. First, the interest region of a barcode image was detected by close operations in morphology. Second, after that, the boundary of the barcode are detected by intersecting four cross line outside in a code. Three, the projected image is then rectified into a two-dimensional barcode in a square shape by the reverse-perspective transform. In result, it shows that our detection and recognition rates for the barcode image is also 97.20% and 94.80%, respectively and that outperforms than previous methods in various illumination and distorted image environments.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.7 no.8
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• pp.1854-1863
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• 2003

In the recent digital communication systems, the performance of Turbo Code using the mr correction coding depends on the interleaver influencing the free distance determination and the recursive decoding algorithms that is executed in the huh decoder. However, performance depends on the interleaver depth that needs many delays over the reception process. Moreover, turbo code has been blown as the robust coding methods with the confidence over the fading channel. International Telecommunication Union(ITU) has recently adopted it as the standardization of the channel coding over the third generation mobile communications(IMT­2000). Therefore, in this paper, we preposed the interleaver that has the better performance than existing block interleaver, and modified turbo decoder that has the parallel concatenated structure using MAP algorithm. In the real­time voice and video service over third generation mobile communications, the performance of the proposed two methods was analyzed and compared with the existing methods by computer simulation in terms of reduced decoding delay using the variable decoding method over AWGN and fading channels for CDMA environments.

• Convergence Security Journal
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• v.15 no.3_1
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• pp.99-105
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• 2015

A typical SRAM-based PUF is used in random number generation and key exchange process. The generated out puts should be preserved, but the values are changed owing to the external environment. This paper presents a new D-PUF logic employing a dual anti-fuse OTP memory to the SRAM-based PUF. The proposed PUF can enhance the reliability of the logic since it can preserve the output values. First, we construct the OTP memory using an anti-fuse. After power up, a SRAM generates the random values owing to the mismatch of cross coupled inverter pair. The generated random values are programed in the proposed anti-fuse ROM. The values that were programed in the ROM at once will not be changed and returned. Thus, the outputs of the proposed D-PUF are not affected by the environment variable such as the operation voltage and temperature variation, etc. Consequently, the reliability of the proposed PUF will be enhanced owing to the proposed dual anti-fuse ROM. Therefore, the proposed D-PUF can be stably operated, in particular, without the powerful ECC in the external environment that are changed.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.11 no.5
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• pp.185-192
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• 2011

In this paper, we simulate and analyze performance of iterative coding scheme, double binary turbo code, for high speed power line communication (PLC) systems. PLC system has hostile environment for high speed data transmission, so error correction method is necessary to compensate effects of PLC channel. We employ the PLC model proposed by M. Zimmerman and Middleton Class A interference model, and system performance is evaluated in terms of bit error rate (BER). From the simulation results, we confirm double binary turbo code provides considerable coding gains to PLC system and BER performance is significantly improved as the number of iteration increase. It is also confirmed that BER performance increases as code rate is lager, while it decreases as the code rate is smaller.

• Journal of the Institute of Electronics and Information Engineers
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• v.54 no.7
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• pp.36-46
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• 2017

The turbo code, an error correction code, needs a long decoding time since the same decoding process must be repeated several times in order to obtain a good BER performance. Thus, parallel processing may be used to reduce the decoding time, in which case there may be a memory contention that requires additional buffers. The QPP interleaving has been proposed to avoid such case, but there is still a possibility of memory contention when a decoder is constructed using the so-called double flow technique. In this paper, we propose an even-odd cross mapping technique to avoid memory conflicts even in decoding using the double-flow technique. This method uses the address generation characteristic of the QPP interleaving and can be used to implement the interleaving circuit between the decoding blocks and the LLR memory blocks. When the decoder implemented by applying the double flow and the proposed methods is compared with the decoder by the conventional MDF techniques, the decoding time is reduced by up to 32% with the total area increase by 8%.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.32 no.8A
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• pp.820-826
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• 2007

This paper proposes an enhanced degree computationless modified Euclid's(E-DCME) algorithm and its architecture for Reed-Solomon decoders. The proposed E-DCME algorithm has shorter critical path delay that is $T_{mult}+T_{add}+T_{mux}$ compared with the existing modified Euclid's algorithm and the degree computationless modified Euclid's(DCME) algorithm since it uses new initial conditions. The proposed E-DCME architecture employing a systolic array requires only 2t-1 clock cycles to solve the key equation without initial latency. In addition, the E-DCME architecture consisting of 3t basic cells has regularity and scalability since it uses only one processing element. The E-DCME architecture using the $0.18{\mu}m$ Samsung standard cell library consists of 18,000 gates.