• Journal of the Institute of Electronics Engineers of Korea SP
• /
• v.42 no.5 s.305
• /
• pp.137-144
• /
• 2005

In this paper, the extraction method of the edge histogram directly using wavelet coefficients in the wavelet domain for JPEG2000 images is proposed. MPEG-7 Edge Histogram Descriptor(EHD) extracts edge histogram in the spacial domain. This algorithm has much multiplication and addition for the edge extraction because it needs the decoding processing. However because the proposed algorithm extracts the edge histogram in the wavelet domain, it doesn't need the decoding processing and it decreases multiplication and addition. The Discrete Wavelet Transform(DWT) is a standard transform in JPEG2000. The proposed algorithm uses Le Gall 5/3 filter in JPEG2000 and odd coefficients in LH2 and HL2 sub-band. The edge direction can be decided to use rate of HL2 and LH2 odd coefficients. According to experiments, there is no difference of the efficiency between EHD and the proposed algorithm And the proposed algorithm is much better than EHD for multiplication and addition in the edge extraction of images.

• Journal of the Institute of Electronics and Information Engineers
• /
• v.53 no.6
• /
• pp.130-136
• /
• 2016

HEVC (High Efficiency Video Coding) extension considers screen content as one of its main candidate sources for encoding. Among the tools already included in HEVC version 1, the technique of using transform skip mode allows transform to be skipped and to perform quantization process only. It is known to improve video coding efficiency for screen contents which are characterized to have much high frequency energy. But encoding complexity increases since its encoder should decide whether transform should be used or not in each $4{\times}4$ transform block. Based on statistical correlation between IBC (Intra block copy) and transform skip modes both of which are known effective in screen contents, this paper proposes a combined method of the fast transform skip mode decision and a modified transform skip signaling which signals transform_skip_flag at CU level as a representative transform skip signal. By simulation, the proposed method is shown to reduce encoding time of $4{\times}4$ transform blocks by about 32%.

• Journal of Broadcast Engineering
• /
• v.19 no.6
• /
• pp.767-788
• /
• 2014

The worldwide transition from analog to digital broadcasting has now been completed and the need to study next generation standards for Ultra High Definition TV (UHDTV) broadcasting, and broadcasting & communication convergence systems is rapidly growing. In particular, high resolution mobile broadcasting services are needed to satisfy recent consumers. Therefore, the development of highly efficient convergence broadcasting systems that provide fixed/mobile broadcasting through a single channel is needed. In this paper, a service scenario and requirements for providing 4K UHD & HD convergence broadcasting services through a terrestrial single channel are analyzed by employing the latest transmission and A/V codec technologies. Optimized transmission parameters for 6 MHz & 8 MHz terrestrial bandwidths are drawn, and receiving performances are measured under Additive White Gaussian Noise (AWGN) and time-varying multipath channels. From the results, in a 6 MHz bandwidth, the reliable receiving of HD layer data can be achieved when the receiver velocity is maximum 140 Km/h and is not achieved when the velocity is over 140 Km/h due to the limit of bandwidth. When the bandwidth is extended to 8 MHz, the reliable receiving of both 4K UHD and HD layer data is achieved under a very fast fading multipath channel.

• Journal of Broadcast Engineering
• /
• v.15 no.3
• /
• pp.426-433
• /
• 2010

The H.264/AVC video coding standard performs inter prediction using variable block sizes to improve coding efficiency. Since we predict not only the motion of homogeneous regions but also the motion of non-homogeneous regions accurately using variable block sizes, we can reduce residual information effectively. However, each motion vector should be transmitted to the decoder. In low bit rate environments, motion vector information takes approximately 40% of the total bitstream. Thus, motion vector competition was proposed to reduce the amount of motion vector information. Since the size of the motion vector difference is reduced by motion vector competition, it requires only a small number of bits for motion vector information. However, we need to send the corresponding index of the best motion vector predictor for decoding. In this paper, we propose a new codeword table based on the phased-in code to encode the index of motion vector predictor efficiently. Experimental results show that the proposed algorithm reduces the average bit rate by 7.24% for similar PSNR values, and it improves the average image quality by 0.36dB at similar bit rates.

• Journal of Broadcast Engineering
• /
• v.10 no.4 s.29
• /
• pp.528-539
• /
• 2005

The H.264 has been adopted as the video codec for various multimedia services such as DMB and next-generation DVD because of its superior coding performance. However, the reference codec of the standard, the joint model (JM) contains quite a few algorithms which are too complex to be used for the resource-constraint embedded environment. This paper introduces very low-complexity H.264 encoding algorithm which is applicable for the embedded environment. The proposed algorithm was realized by restricting some coding tools on the basis that it should not cause too severe degradation of RD-performance and adding a few early termination and bypass conditions during the motion estimation and mode decision process. In case of encoding of 7.5fps QCIF sequence with 64kbpswith the proposed algorithm, the encoder yields worse PSNRs by 0.4 dB than the standard JM, but requires only $15\%$ of computational complexity and lowers the required memory and power consumption drastically. By porting the proposed H.264 codec into the PDA with Intel PXA255 Processor, we verified the feasibility of the H.264 based MMS(Multimedia Messaging Service) on PDA.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.10 no.7
• /
• pp.1172-1179
• /
• 2006

Recently, the H.264/AVC, which was standardized jointly by ISO/IEC and ITU-T, has been expanding its applications in various areas. This standard includes many advanced component techniques compared to the existing MPEG techniques. Intra prediction which is to predict the spatial data in an intra frame in one of them. But it has a serious defect that it needs large amount of calculation. To overcome this defect, this paper proposed a method to reduce about 60% of the amount of calculation with only O.02dB of image quality degradation. This method determines the calculation directly without much pre-calc cluation process by referring the left block(s) and upper blocks(s) that were processd already. Comparing to the exi sting methods, its image quality degradation is so small that it is expected to be used in many areas. Especially in the wireless appliances such as DMB phone which has restricted power source, we expect it would be used efficiently.

• Journal of the Institute of Electronics Engineers of Korea SP
• /
• v.44 no.3
• /
• pp.23-32
• /
• 2007

The H.264/AVC video coding standard uses rate distortion optimization (RDO) method to improve the compression performance in the intra prediction. The complexity and computational load are increased more than previous standard by using this method, even though this standard selects the best coding mode for the current macroblock. This paper proposes a fast intra mode decision algorithm for H.264/AVC encoder based on dominant edge direction (DED). To apply the idea, this algorithm uses the approximation of discrete cosine transform (DCT) coefficient. By detecting the DED, 3 modes instead of 9 modes are chosen for RDO calculation to decide the best mode in the $4{\times}4$ luma block. As for the $16{\times}16$ luma and $8{\times}8$ chroma block, instead of 4 modes, only 2 modes are searched. Experimental results show that the computation time of the proposed algorithm is decreased to about 72% of the full search method with negligible quality loss.

• Journal of the Institute of Convergence Signal Processing
• /
• v.9 no.4
• /
• pp.321-328
• /
• 2008

In this paper, we propose the hardware architecture of two-dimensional discrete wavelet transform (2D DWT) and quantization for using JPEG2000. Color 2-D DWT processor is proposed that is to apply to JPEG 2000 Hard-wired Encoder. JPEG 2000 DWT processor uses the Daubechies' (9,7) bi-orthogonal filter, and we design by minimizing error of the DWT transformer by ${\pm}1$ LSB during compression and decompression. We designed the DWT filters that using by using shift and adder structure instead of multiplier structure which raise the hardware complexity. It is improve the operation speed of filters and reduce the hardware complexity. The proposed system is designed by the hardware description language Verilog-HDL and verified by Synopsys Design Analyzer using TSMC 0.25${\mu}m$ ASIC library.

• Journal of Korea Multimedia Society
• /
• v.12 no.2
• /
• pp.200-208
• /
• 2009

JBIG2, as the next generation standard for binary image compression, must be designed in hardware modules for the JBIG2 FAX to be implemented in an embedded equipment. This paper proposes a hardware module of the high-speed Huffman coder for JBIG2. The Huffman coder of JBIG2 uses selectively 15 Huffman tables. As the Huffman coder is designed to use minimal data and have an efficient memory usage, high speed processing is possible. The designed Huffman coder is ported to Virtex-4 FPGA and co-operating with a software modules on the embedded development board using Microblaze core. The designed IP was successfully verified using the simulation function test and hardware-software co-operating test. Experimental results shows the processing time is 10 times faster than that of software only on embedded system, because of hardware design using an efficient memory usage.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.21 no.4
• /
• pp.774-780
• /
• 2017

This paper proposes an efficient binary arithmetic encoder hardware architecture for CABAC encoding, which is an entropy coding method of HEVC. CABAC is an entropy coding method that is used in HEVC standard. Entropy coding removes statistical redundancy and supports a high compression ratio of images. However, the binary arithmetic encoder causes a delay in real time processing and parallel processing is difficult because of the high dependency between data. The operation of the proposed CABAC BAE hardware structure is to separate the renormalization and process the conventional iterative algorithm in parallel. The new scheme was designed as a four-stage pipeline structure that can reduce critical path optimally. The proposed CABAC BAE hardware architecture was designed with Verilog HDL and implemented in 65nm technology. Its gate count is 8.07K and maximum operating speed of 769MHz. It processes the four bin per clock cycle. Maximum processing speed increased by 26% from existing hardware architectures.