• The Journal of Korean Institute of Communications and Information Sciences
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• v.37A no.11
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• pp.993-1000
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• 2012

In this research, we proposed an efficient VLSI architecture of the lifting-based 2D DWT (Discrete Wavelet Transform) filter with 100% hardware utilization. The (9,7) filter structure has been applied and extendable to the filter length. We proposed a new block-based scheduling that computes the DWT for the lower levels on an "as-early-as-possible" basis, which means that the calculation for the lower level will start as soon as the data is ready. Since the proposed 2D DWT computes the outputs of all levels by one row-based scan, the intermediate results for other resolution levels should be kept in storage such as the Data Format Converter (DFC) and the Delay Control Unit (DCU) until they are used. When the size of input image is $N{\times}N$ and m is the filter length, the required storage for the proposed architecture is about 2mN. Since the proposed architecture processes the 2D DWT in horizontal and vertical directions at the same time with 4 input data, the total period for 2D DWT is $N^2(1-2^{-2J})/3$.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.21 no.4
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• pp.774-780
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• 2017

This paper proposes an efficient binary arithmetic encoder hardware architecture for CABAC encoding, which is an entropy coding method of HEVC. CABAC is an entropy coding method that is used in HEVC standard. Entropy coding removes statistical redundancy and supports a high compression ratio of images. However, the binary arithmetic encoder causes a delay in real time processing and parallel processing is difficult because of the high dependency between data. The operation of the proposed CABAC BAE hardware structure is to separate the renormalization and process the conventional iterative algorithm in parallel. The new scheme was designed as a four-stage pipeline structure that can reduce critical path optimally. The proposed CABAC BAE hardware architecture was designed with Verilog HDL and implemented in 65nm technology. Its gate count is 8.07K and maximum operating speed of 769MHz. It processes the four bin per clock cycle. Maximum processing speed increased by 26% from existing hardware architectures.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2015.05a
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• pp.93-96
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• 2015

In this paper, we introduce a fire detection system using context-aware sensor. In existing weather and based on vision sensor of fire detection system case, acquired image through sensor of camera is extracting features about fire range as processing to convert HSI(Hue, Saturation, Intensity) model HSI which is color space can have durability in illumination changes. However, in this case, until a fire occurs wide range of sensing a fire in a single camera sensor, it is difficult to detect the occurrence of a fire. Additionally, the fire detection in complex situations as well as difficult to separate continuous boundary is set for the required area is difficult. In this paper, we propose an algorithm for real-time by using a temperature sensor, humidity, Co2, the flame presence information acquired and comparing the data based on multiple conditions, analyze and determine the weighting according to fire it. In addition, it is possible to differential management to intensive fire detection is required zone dividing the state of fire.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.34 no.12B
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• pp.1418-1425
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• 2009

This paper proposes a novel FTL (Flash Translation Layer) algorithm based on sector-level mapping to reduce the number of total erase operations in flash memory accesses. The proposed algorithm can reduce the number of erase operations by utilizing the sector-level mapping table when writing data at flash memory. Sector-level mapping technique reduces flash memory access time and extendsthe life time of the flash memory. In the algorithm, wear-leveling is implemented by selecting victim blocks having the minimal number of erase operations, when empty spaces for write are not available. To evaluate the performance of the proposed FTL algorithm, experiments were performed on several applications, such as MP3 players, MPEG players, web browsers and document editors. The proposed algorithm reduces the number of erase operations by 72.4% and 61.9%, when compared with well-known BAST and FAST algorithms, respectively.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.13 no.2
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• pp.171-179
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• 2013

Recognition and image processing technology depends on illumination variation. One of the most important factors is the parameters of algorithms. When it comes to select these values, the system has different types of recognition accuracy. In this paper, we propose performance improvement of the eye tracking system that depends on some environments such as, people, location, and illumination. Optimized threshold parameter was decided by using reinforcement learning. When the system accuracy goes down, reinforcement learning used to train the value of parameters. According to the experimental results, the performance of eye tracking system can be improved from 3% to 14% by using reinforcement learning. The improved eye tracking system can be effectively used for human-computer interaction.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.17 no.7
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• pp.1618-1626
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• 2013

Virtualization service processes all operation including the data creation, storing, and disposal in a server and transmits processed data as the streaming media form. Therefore, client can use the same environment as the traditional desktop environment without considering the type of device. Virtualization service should consider not only the video quality but also the delay bounds and continuity of video playback for improving the user perceived Quality of Service(QoS) of streaming service. In this paper, we propose a network-adaptive transmission architecture that focuses on guaranteeing QoS requirements for virtualization service. In order to provide those, the proposed architecture have the transmission rate adaptation function based on available bandwidth and the content bit-rate control function based on sender buffer state. Through each function, proposed architecture guarantee the delay bounds and continuity of virtualization contents playback. The simulation results show that proposed network-adaptive transmission architecture provides a improve performance of throughput and transmission delay.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2007.10a
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• pp.119-122
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• 2007

In this paper, we propose the method of hardware-design for the division operation of image frame-unit processing in mobile phone camera. Generally, there are two types of the data processing, which are the parallel and serial type. The parallel type makes it possible to process in realtime, but it needs significant hardware size due to many comparators and buffer memories. Compare the serial type with the parallel type, the hardware size of the serial type is smaller than the other because it uses only one comparator, but serial type is not able to process in realtime. To use the hardware resources efficiently, we employ the serial divider since frame-unit operation for image processing does not need realtime process. When compared with both in the same bit size and operating frequency, the hardware size of the serial divider is approximately in the ratio of 13 percentage compared with the parallel divider.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.17 no.4
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• pp.953-958
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• 2013

In this paper, an efficient hardware architecture is proposed for $32{\times}32$ inverse transform HEVC decoder. HEVC is a new image compression standard to deal with much larger image sizes compared with conventional image codecs, such as 4k, 8k images. To process huge image data effectively, it adopts various new block structures. Theses blocks consists of $4{\times}4$, $8{\times}8$, $16{\times}16$, and $32{\times}32$ block. This paper suggests an effective structures to process $32{\times}32$ inverse transform. This structure of inverse transform adopts the decomposed $16{\times}16$ matrixes of $32{\times}32$ matrix, and simplified the operations by implementing multiplying with shifters and adders. Additionally the operations frequency is downed by using multicycle paths. Also this structure can be easily adopted to a multi-size transform or a forward transform block in HEVC codec.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.35 no.11A
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• pp.1059-1065
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• 2010

Recently, analog broadcasting are being converted into digital radio broadcasts, Among the various ways that HD Radio is a candidate for the U.S. approach, Digital Radio will transmit a digital signal to existing analog FM/AM. It provides clear sound quality, traffic information, weather information and various value-added services. In addition, the converted digital radio will be able to meet demand to growing demand for analog FM. In this paper, Digital FM Radio system in the same frequency band using electric field strength of the received digital radio broadcasting interference effects were analyzed. And Digital FM Radio Receiver interference effects were analyzed by interference signal power and signal power. Results were confirmed by applying equation at minimum field strength and SNR.

• The Transactions of the Korea Information Processing Society
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• v.6 no.1
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• pp.193-202
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• 1999

A promising telecommunication system so called IMT-2000 is forecasted to cover almost 50 percent of telecommunication services, which will be provided in the beginning of the year 2000. The system offers high quality service such as data, image, and video as well as voice. UPT, which offers the personal mobility, is recognized as an important service because we can bind a variety of wire or wireless networks as single number. This paper discusses the design of IMT-2000 MSC based on AIN and UPT service in the MSC. First, we propose the system structure of the IMP-2000 MSC, as a platform of UPT service implementation. Based on this, we define main functions and its blocks of the IMP-2000 MSC. Third, we present the structure of SSF and Its operational mechanism to support the IN services such as UPT. Finally, we present the detail UPT service implementation for the IMP-2000 MSC through the design of UPT call flows between software blocks, which are the minimum units, within the IMPt-2000 MSC.