• Journal of the Korea Society of Computer and Information
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• v.10 no.3 s.35
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• pp.151-159
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• 2005

Traditional watermarking technologies are symmetric method which embedding and detection keys are same. Although the symmetric watermarking method is easy to detect the watermark, this method has weakness against to malicious attacks to remove or modify the watermark information when the symmetric key is disclosure. Recently, the asymmetric watermarking method that has different keys to embed and detect is watched several researchers as a next generation watermarking technology. In this paper, we have expanded search space of secret key using the solution set of linear simultaneous equations. Secret key is generated by secure linear transformation method to prevent of guessing secret key from public key, and the correlation value between secret key and public key is high. At theresults, the multi bits information can be embedded and high correlation value was detected after JPEG compression.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.30 no.2C
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• pp.49-58
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• 2005

For the improvement of coding efficiency, the H.264 standard uses new coding tools. Using these coding tools, H.264 has achieved significant improvements from rate-distortion point of view. The adoption of these tools enables a macroblock in H.264 to have more information, sixteen motion vectors, four reference frames and a macroblock mode. In this paper, we present an efficient temporal error concealment algorithm by using not only motion vectors and reference frames but also macroblock mode of neighbor macroblocks. Our algorithm conceals the macroblock error with variable sizes, $16{\times}16,\;16{\times}8,\;8{\times}16,\;8{\times}8$ depending on the macroblock modes of neighbor macroblocks. Simulation results show that the proposed method increase the objective quality regardless of bit-rate and block error rate.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• v.9 no.2
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• pp.595-598
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• 2005

MPEG-4 Visual is, and international standard for the object-based video compression, designed for supporting a wide range of applications from multimedia communication to HDTV. To control the minimum decoding complexity required at the decoder, the MPEG-4 Visual standard defines the co-called video buffering mechanism, which includes three video buffer models. Among them, the VCV(Video Complexity Verifier) defines the control of the processing speed for decoding of a macroblock, there are two models: VCV and B-VCV distinguishing the boundary and non-boundary MB. This paper presents the evaluation results of decoding complexity by measuring decoding time of a MB for rectangular, arbitrarily shaped video objects and the various types of objects supporting the resolution of HDTV using the optimized MPEG-4 Reference Software. The experimental results shows that decoding complexity varies depending on the coding type and more effective usage of decoding resources may be possible.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.29 no.11C
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• pp.1541-1550
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• 2004

In this paper, we propose an advanced hardware architecture for fast multi-resolution motion estimation of the video coding standard MPEG-1,2 and MPEG-4 AVC. We describe the algorithm and derive hardware architecture emphasizing the importance of area for low cost and fast operation by using the shared memory, the special ram architecture, the motion vector for 4 pixel x 4 pixel, the spiral search and so on. The proposed architecture has been verified by ARM-interfaced emulation board using Excalibur Altera FPGA and also by ASIC synthesis using Samsung 0.18 m CMOS cell library. The ASIC synthesis result shows that the proposed hardware can operate at 140 MHz, processing more than 1,100 QCIF video frames or 70 4CIF video frames per second. The hardware is going to be used as a core module when implementing a complete MPEG-4 AVC video encoder ASIC for real-time multimedia application.

• The KIPS Transactions:PartC
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• v.12C no.3 s.99
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• pp.379-386
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• 2005

Traditional watermarking technologies are symmetric method which embedding and detection keys are same. Although the symmetric watermarking method is easy to detect the watermark, has method has weakness against to malicious attacks to remove or modify the watermark information when the symmetric key is disclosure. Recently, the asymmetric watermarking method that has different keys to embed and detect is watched several researchers as a next generation watermarking technology. In this paper, we have expanded search space of secret key using the solution set of linear simultaneous equations. Secret key is generated by secure linear transformation method to prevent of guessing secret key from public key, and the correlation value between secret key and public key is high. At the results, the multi bits information can be embedded and high correlation value was detected after JPEG compression.

• Journal of the Institute of Convergence Signal Processing
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• v.5 no.2
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• pp.126-131
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• 2004

Full search algorithm(FA) provides the best performance but this is usually impractical because of the large number of computations required for large search region. Fast search and conventional Boolean matching algorithms reduce computational complexity and data processing time but this algorithms have disadvantages that is difficult of implementation of hardware because of high control overhead and that is less performance than FA. This paper presents new Boolean matching algorithm, called BCBM(Bit Converted Boolean Matching). Proposed algorithm has performance closed to the FA by Boolean only block matching that may be very efficiently implemented in hardware for real time video communication. Simulation results show that the PSNR of the proposed algorithm is about 0.08㏈ loss than FA but is about 0.96∼2.02㏈ gain than fast search algorithm and conventional Boolean matching algorithm.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.22 no.8
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• pp.1790-1802
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• 1997

A wavelet transform coding method that fulfills the requirements of HD-VCR(high definition video casstte recorder) for studio applications in proposed. A constant bit rate is achieved by a forward rate control technique whcih determins the quantizer stepsize based on the coding results fo the previous frame. We also propose a two-level coder that consists of both the IDC(independently decodable code) and the DDC(dependently decodable code). To minimize error propagation, the transformed coefficients are restructured into transform blocks which are represented by a tree structure. The result shows thta the proposed coding scheme produces better picture quality with block effects than that of DCT(discrete cosine transform) based coding schemes at the same compression ratio. The proposed method meets most of the requirements of HD-VCR.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.19 no.4
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• pp.772-780
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• 1994

Vector quantization with two-channel conjugate codebook has been researched as an efficient coding technique that can reduce the computational complexity and codebook storage. This paper proposes FSVQ using two-channel conjugate codebook in order to reduce the number of state codebooks. Input vector in the two-channel conjugate FSVQ is coded with state codebook of a seperated state according to each codebook. In addition, LOT is adopted to obtain to obtain a high coding gain and to reduce blocking effect which appears in the block coding. As a result, although FSVQ can achieve higher data compression ratio than general vector quantization, it has a disadvantage of having a very large number of state codebooks. However FSVQ with two-channel conjugate codebooks can employ a significantly reduced number of state codebooks, even though it has a small loss in the PSNR compared with the conventional FSVQ using one codebook. Moreover FSVQ in the LOT domain can reduce blocking effect and high coding gain compared with FSVQ in the spatial domain.

• Broadcasting and Media Magazine
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• v.11 no.4
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• pp.118-131
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• 2006

With rapid development in ultra fast communication and digital multimedia, the realistic broadcasting technology, that can stimulate five human senses beyond the conventional audio-visual service is emerging as a new generation broadcasting technology. In this paper, we introduce a haptic broadcasting system and related core system and component techniques by which we can 'touch and feel' objects in an audio-visual scene. The system is composed of haptic media acquisition and creation, contents authoring, in the haptic broadcasting, the haptic media can be 3-D geometry, dynamic properties, haptic surface properties, movement, tactile information to enable active touch and manipulation and passive movement following and tactile effects. In the proposed system, active haptic exploration and manipulation of a 3-D mesh, active haptic exploration of depth video, passive kinesthetic interaction, and passive tactile interaction can be provided as potential haptic interaction scenarios and a home shopping, a movie with tactile effects, and conducting education scenarios are produced to show the feasibility of the proposed system.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2017.10a
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• pp.543-545
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• 2017

This paper describes the SAO hardware architecture design for high performance in-loop filters. SAO is an inner module of in-loop filter, which compensates for information loss caused by block-based image compression and quantization. However, HEVC's SAO requires a high computation time because it performs pixel-unit operations. Therefore, the SAO hardware architecture proposed in this paper is based on a $4{\times}4$ block operation and a 2-stage pipeline structure for high-speed operation. The information generation and offset computation structure for SAO computation is designed in a parallel structure to minimize computation time. The proposed hardware architecture was designed with Verilog HDL and synthesized with TSMC chip process 130nm and 65nm cell library. The proposed hardware design achieved a maximum frequency of 476MHz yielding 163k gates and 312.5MHz yielding 193.6k gates on the 130nm and 65nm processes respectively.