• Journal of Korea Spatial Information System Society
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• v.4 no.1 s.7
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• pp.39-46
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• 2002

In distributed spatial database systems, users nay issue a query that joins two relations stored at different sites. The sheer volume and complexity of spatial data bring out expensive CPU and I/O costs during the spatial join processing. This paper shows a new spatial join method which joins two spatial relation in a parallel way. Firstly, the initial join operation is divided into two distinct ones by partitioning one of two participating relations based on the region. This two join operations are assigned to each sites and executed simultaneously. Finally, each intermediate result sets from the two join operations are merged to an ultimate result set. This method reduces the number of spatial objects participating in the spatial operations. It also reduces the scope and the number of scanning spatial indices. And it does not materialize the temporary results by implementing the join algebra operators using the iterator. The performance test shows that this join method can lead to efficient use in terms of buffer and disk by narrowing down the joining region and decreasing the number of spatial objects.

• School Mathematics
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• v.13 no.3
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• pp.405-422
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• 2011

In this study, we consider the meaning of one-to-one correspondence through theoretical background under operation of matrix. On algebraic point of view, its significance is 'through one-to-one correspondence from a set with given structure, become a methods in order to induce an algebraic system in to a new set.' That is a key idea making isomorphic structure. Such process experiences necessity of mathematical fact, as well as the deep understanding of one-to-one correspon -dence. Also that becomes a base for develop a various mathematical concepts, such as matrix, exponential laws, symmetric difference, permutation and so on. This study help teachers and students to understand of mathematical concepts meaningfully and to facilitate teacher's professional development.

• Journal of IKEEE
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• v.22 no.3
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• pp.522-531
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• 2018

A public-key cryptography processor EC-RSA was designed, which integrates a 224-bit prime field elliptic curve cryptography (ECC) defined in the FIPS 186-2 as well as RSA with 2048-bit key length into a single hardware structure. A finite field arithmetic core used in both scalar multiplication for ECC and exponentiation for RSA was designed with 32-bit data-path. A lightweight implementation was achieved by an efficient hardware sharing of the finite field arithmetic core and internal memory for ECC and RSA operations. The EC-RSA processor was verified by FPGA implementation. It occupied 11,779 gate equivalents (GEs) and 14 kbit RAM synthesized with a 180-nm CMOS cell library and the estimated maximum clock frequency was 133 MHz. It takes 867,746 clock cycles for ECC scalar multiplication resulting in the estimated throughput of 34.3 kbps, and takes 26,149,013 clock cycles for RSA decryption resulting in the estimated throughput of 10.4 kbps.

• Journal of KIISE:Computer Systems and Theory
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• v.36 no.6
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• pp.543-556
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• 2009

Recently, NAND flash memory is being used as the swap device of virtual memory as well as the file storage of mobile systems. Since temporal locality is dominant in page references of virtual memory, LRU and its approximated CLOCK algorithms are widely used. However, cost of a write operation in flash memory is much larger than that of a read operation, and thus a page replacement algorithm should consider this factor. This paper analyzes virtual memory read/write reference patterns individually, and observes the ranking inversion problem of temporal locality in write references which is not observed in read references. With this observation, we present a new page replacement algorithm considering write frequency as well as temporal locality in estimating write reference behaviors. This new algorithm dynamically allocates memory space to read/write operations based on their reference patterns and I/O costs. Though the algorithm has no external parameter to tune, it supports optimized implementations for virtual memory systems, and also performs 20-66% better than CLOCK, CAR, and CFLRU algorithms.

• Journal of KIISE:Computer Systems and Theory
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• v.36 no.5
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• pp.422-428
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• 2009

NAND flash memory is widely used in embedded systems because of many attractive features, such as small size, light weight, low power consumption and fast access speed. However, it requires garbage collection, which includes erase operations. Erase operation is slower than other operations. Further, a block has a limited erase lifetime (typically 100,000) after which a block becomes unusable. The proposed garbage collection policy focuses on minimizing the total number of erase operations, the deviation value of each block and the garbage collection time. NAND flash memory consists of pages of three types, such as valid pages, invalid pages and free pages. In order to achieve above goals, we use a page ratio to decide when to do garbage collection and to select the target victimblock. Additionally, we implement allocating method and group management method. Simulation results show that the proposed policy performs better than Greedy or CAT with the maximum rate 85% of reduction in the deviation value of the erase operations and 6% reduction in garbage collection time.

• KIPS Transactions on Software and Data Engineering
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• v.6 no.12
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• pp.573-580
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• 2017

Deep Neural Network (DNN) is a large layered neural network which is consisted of a number of layers of non-linear units. Deep Learning which represented as DNN has been applied very successfully in various applications. However, many issues in DNN have been identified through past researches. Among these issues, generalization is the most well-known problem. A Recent study, Dropout, successfully addressed this problem. Also, Dropout plays a role as noise, and so it helps to learn robust feature during learning in DNN such as Denoising AutoEncoder. However, because of a large computations required in Dropout, training takes a lot of time. Since Dropout keeps changing an inter-layer representation during the training session, the learning rates should be small, which makes training time longer. In this paper, using mutation operation, we reduce computation and improve generalization performance compared with Dropout. Also, we experimented proposed method to compare with Dropout method and showed that our method is superior to the Dropout one.

• Journal of Korea Society of Industrial Information Systems
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• v.23 no.4
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• pp.13-22
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• 2018

In this paper, double encryption technology of image based on scramble operation and phase-shifting digital holography is proposed. For the purpose, we perform first encryption digitally using scramble operation for the to be encrypted image, and perform phase modulation to the first encrypted image. Finally, we get the secondary encryption information through the interference between the phase-shifted reference wave and phase modulated image. The decryption process proceeds in the reverse order of the encryption process. The original image is reconstructed by digitally decoding the two encrypted images through a phase shift digital holography technique that appropriately performs arithmetic processing, phase-demodulating and then using the encryption key information used in the scramble operation. The proposed cryptosystem can recover the original image only if both the key information used in the scramble operation, the distance information used in the phase shift digital holography technique, and the wavelength of the light source are known accurately.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.10 no.11
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• pp.3087-3093
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• 2009

Digital filters are indispensible element in digital signal processing area. The performance of digital filter based on adding and multiplying operation, such as computational speed and power consuming is determined by the orders and coefficients of filter which has on effect area of semiconductor chip when it is implemented by VLSI technology. In this research, in order to performance improvement of digital filter, we proposed the algorithm to speed-up the operation of digital filter associated with the minimum signed digit representation of binary number system and method to simplify the digital filter design associated with common subexpression elimination. The performance of proposed method is evaluated by the computational speed and design-simplicity by experimental implemented digital filter on FPGA.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.5
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• pp.112-120
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• 2013

In this paper, we propose high-performance H.264/AVC CAVLC encoder for UD video real time processing. Statistical values are obtained in one cycle through the parallel arithmetic and logical operations, using non-zero bit stream which represents zero coefficient or non-zero coefficient. To encode codeword per one cycle, we remove recursive operation in level encoding through parallel comparison for coefficient and escape value. In oder to implement high-speed circuit, proposed CAVLC encoder is designed in two-stage {statical scan, codeword encoding} pipeline. Reducing the encoding table, the arithmetic unit is used to encode non-coefficient and to calculate the codeword. The proposed architecture was simulated in 0.13um standard cell library. The gate count is 33.4Kgates. The architecture can support Ultra Definition Video ($3840{\times}2160$) at 100 frames per second by running at 100MHz.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.27 no.3
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• pp.477-487
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• 2017

Multiparty computation (MPC) is a computation technique where many participants provide their data and jointly compute operations to get a computation result. Earlier MPC protocols were mostly depended on communication between the users. Several schemes have been presented that mainly work by delegating operations to two non-colluding servers. Peter et al. propose a protocol that perfectly eliminates the need of users' participation during the whole computation process. However, the drawback of their scheme is the excessive dependence on the server communication. To cater this issue, we propose a protocol that reduce server communication overhead using the proxy re-encryption (PRE). Recently, some authors have put forward their efforts based on the PRE. However, these schemes do not achieve the desired goals and suffer from attacks that are based on the collusion between users and server. This paper, first presents a comprehensive analysis of the existing schemes and then proposes a secure and efficient MPC protocol. The proposed protocol completely eliminates the need of users' participation, incurs less communication overhead and does not need to solve the discrete logarithm problem (DLP) in order to get the computation results.