• Journal of KIISE:Software and Applications
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• v.27 no.11
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• pp.1073-1081
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• 2000

본 연구에서는 효과적인 시계열 예측을 위하여 구간연산 기능을 갖는 신경망모델을 제안한다. 이는 기존의 FIR 네트워크의 동작특성을 구간연산으로 일반화함으로써 시계열 신호의 동적 특성을 효과적으로 반영할 뿐만 아니라 학습데이타 표현의 유연성을 증대시킨다. 이는 또한 실제 응용에서 신경망 입력 데이타에 내재할 수 있는 측정치 오류의 영향을 보완할 수 있게 하며 데이타 그룹화를 효과적으로 이룰 수 있게 함으로써 입력데이타의 양을 감축시키고 이로부터 학습의 효율을 개선한다. 본 논문에서는 구간연산을 이용하여 네트워크 동작특성, 학습알고리즘을 제시하고 실제 응용시스템에 이를 적용함으로써 제안된 이론의 유용성을 평가한다.

• Proceedings of the Korea Information Processing Society Conference
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• 2001.04a
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• pp.271-274
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• 2001

바이패싱 회로는 명령어의 파이프라인의 실행 단계가 종료되자마자 연산 결과를 다음 번 파이프라인 단계의 실행 단계의 실행 유니트에서 사용할 수 있어 명령어 실행 시간이 단축된다. 그러나 바이패싱 회로의 복잡도는 연산처리기가 늘어남에 따라 크게 증가하는 단점이 있으므로 명령어 중복 할당 기법을 적용하면 여러 개의 연산처리기에서 동일한 연산을 수행하여 VLIW 구조에서 가상의 바이패싱 회로가 존재하는 것과 같은 효과를 얻을 수 있다.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.10 no.1
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• pp.89-97
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• 2000

공개키 암호 시스템 중에서 가장 널리 사용되는 RSA 암호 시스템은 키의 분배와 권리가 용이하고, 디지털 서명이 가능한 장점이 있으나, 암호화와 복호화 과정에서 512 비트 이상의 큰 수에 대한 멱승과 모듈라 감소 연산이 요구되기 때문에 처리 속도의 지연이 큰 문제가 되므로 모듈라 멱승 연산의 고속 처리가 필수적이다. 따라서 본 논문에서는 몫을 추정하여 중간 곱의 크기를 제한하는 interleaved 모듈라 곱셈 기법을 이용하여 모듈라 멱승 연산을 수행하는 고속 RSA 암호 칩을 VHDL을 이용하여 모델링하고 Faraday FG7000A 라이브러리를 이용하여 합성하고 타이밍 검증하여 단일 칩 IC로 구현하였다. 구현된 암호 칩은 75,000 게이트 수준으로 합성되었으며, 동작 주파수는 50MHz이고 1회의 RSA 연산을 수행하는데 소요되는 전체 클럭 사이클은 0.25M이며 512비트 당 처리 속도는 102.4Kbit/s였다.

• KIPS Transactions on Computer and Communication Systems
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• v.4 no.12
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• pp.391-398
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• 2015

This paper devises a performance improvement and evaluation process of circuit minimization algorithms for mentorship education of distinguished informatics gifted secondary students. In the process, students learn that there are several alternative equivalent circuits for a target function and recognize the necessity for formalized circuit minimization methods. Firstly, they come at the concept of circuit minimization principle from Karnaugh Map which is a manual methodology. Secondly, they explore Quine-McCluskey algorithm which is a computational methodology. Quine-McCluskey algorithm's time complexity is high because it uses set operations. To improve the performance of Quine-McCluskey algorithm, we encourage them to adopt a bit-wise data structure instead of integer array for sets. They will eventually see that the performance achievement is about 36%. The ultimate goal of the process is to enlarge gifted students' interest and integrated knowledge about computer science encompassing electronic switches, logic gates, logic circuits, programming languages, data structures and algorithms.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.25 no.8
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• pp.1060-1066
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• 2021

Recently, researches for quantum computers have been carried out in various fields. Quantum computers performs calculations by utilizing various phenomena and characteristics of quantum mechanics such as quantum entanglement and quantum superposition, thus it is a very complex calculation process compared to classical computers used in the past. In order to simulate a quantum computer, many factors and parameters of a quantum computer need to be analyzed, for example, error verification, optimization, and reliability verification. Therefore, it is necessary to visualize circuits that can intuitively simulate the configuration of the quantum computer components. In this paper, we present a novel visualization method for designing complex quantum computer system, and attempt to create a 3D visualization toolkit to deploy large circuits, provide help a new way to design large-scale quantum computing systems that can be built into future computing systems.

• Journal of KIISE:Databases
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• v.28 no.3
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• pp.494-511
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• 2001

In the environment that database management systems manage disk spaces for storing databases directly, this paper proposes a correct and efficient scheme of performing pending actions for the removal of database files. As for performing pending actions, upon performing recovery, the recovery process must identify unperformed pending actions of not-yet-terminated transactions and then perform those actions completely. Making the recovery process identify those actions through the analysis of log records in the log file is the basic idea of this paper. This scheme, as an extension of the execution of transactions, fuzzy checkpoint, and recovery of ARIES, uses the following methods: First, to identify not-yet-terminated transactions during recovery, transactions perform pending actions after writing 'pa_start'log records that signify both the commit of transactions and the start of executing pending actions, and then write 'eng'log records. Second, to restore pending-actions-lists of not-yet-terminated transactions during recovery, each transaction records its pending-actions-list in 'pa_start'log record and the checkpoint process records pending-actions-lists of transactions that are decided to be committed in 'end_chkpt'log record. Third, to identify the next pending action to perform during recovery, whenever a page is updated during the execution of pending actions, transactions record the information that identifies the next pending action to perform in the log record that has the redo information against the page.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.39 no.2
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• pp.123-131
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• 2002

In this paper, a new standard basis parallel ternary-valued multiplier circuit designed using current mode CMOS is presented. Prior to constructing the GF(3$^{ｍ}$) multiplier circuit, we provide a GF(3) adder and a GF(3) multiplier with truth tables and symbolize them, and also design them using current mode CMOS circuit. Using the basic ternary operation concept, a ternary adder and a multiplier, we develop the equations to multiply arbitrary two elements over GF(3$^{ｍ}$). Following these equations, we can design a multiplier generalized to GF(3$^{ｍ}$). For the proposed circuit in this paper, we show the example in GF(3$^{3}$). In this paper, we assemble the operation blocks into a complete GF(3$^{ｍ}$) multiplier. Therefore the proposed circuit is easy to generalize for m and advantageous for VLSI. Also, it need no memory element and the latency not less fewer than other circuit. We verify the proposed circuit by functional simulation and show its result.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.8 no.5
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• pp.1050-1057
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• 2004

The purpose of study is development of a fuzzy controller which independent of a computer and its software for fuzzy control of servo system. This paper describes a method of approximate reasoning for fuzzy control of servo system, based on decomposition of $\alpha$-level fuzzy sets, It is propose that fuzzy logic algorithm is a body from fuzzy inference to defuzzificaion in cases where the output variable u directly is generated PWM. The effectiveness of quantified $\alpha$-levels on input/output characteristics of fuzzy controller and output response of DC servo system is investigated. It is concluded that $\alpha$-cut 4 levels give a sufficient result for fuzzy control performance of DC servo system. The experimental results shows that the proposed hardware method is effective for practical applications of DC servo system.

• Journal of the Institute of Electronics Engineers of Korea CI
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• v.43 no.4 s.310
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• pp.23-30
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• 2006

This paper presents design andd verification of a circuit that improves the control-operation problems of Stored Program Optical Computer (SPOC), which is an optical computer using $LiNbO_3$ optical switching element. Since the memory of SPOC takes the Delay Line Memory (DLM) architecture and instructions that are needless of operands should go though memory access stages, SPOC memory have problems; it takes immoderate access time and unnecessary operations are executed in Arithmetic Logical Unit (ALU) because desired operations can't be selectively executed. In this paper, improvement on circuit has been achieved by removing the memory access of instructions that are needless of operands by decoding instructions before locating operand. Unnecessary operations have been reduced by sending operands to some specific operational units, not to all the operational units in ALD. We show that total execution time of a program is minimized by using the Dual Instruction Register(DIR) architecture.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.40 no.6
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• pp.24-30
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• 2003

This study focuses on the arithmetical methodology and hardware implementation of low system-complexity A $B^2$＋C operator over GF(2$^{m}$ ) using the irreducible AOP of degree m. The proposed parallel-in parallel-out operator is composed of CS, PP, and MS modules, each can be established using the array structure of AND and XOR gates. The proposed multiplier is composed of (m＋1)$^2$ 2-input AND gates and (m＋1)(m＋2) 2-input XOR gates. And the minimum propagation delay is $T_{A}$ ＋(1＋$\ulcorner$lo $g_2$$^{m}$ $\lrcorner$) $T_{x}$ . Comparison result of the related A $B^2$＋C operators of GF(2$^{m}$ ) are shown by table, It reveals that our operator involve more lower circuit complexity and shorter propagation delay then the others. Moreover, the interconnections of the out operators is very simple, regular, and therefore well-suited for VLSI implementation.