• Journal of the Institute of Electronics and Information Engineers
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• v.52 no.6
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• pp.57-61
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• 2015

This paper proposes a fast intra prediction algorithm for the High Efficiency Video Coding (HEVC). HEVC has 35 modes, such as DC mode, Planar mode, and 33 angular modes for the intra-prediction. To reduce the complexity and to support fast decision for intra prediction, this paper proposes a hierarchical mode decision method (HMD). The proposed HMD mainly focuses on how to reduce the number of prediction modes. The experimental results show that the proposed HMD can reduce the encoding time about 39.17% with little BDBR loss. On average, the proposed HMD can achieve the encoding time saving e about 14.13 ~ 19.37% compared to that of the existing algorithms with slightly increasing 0.01 ~ 0.42% BDBR.

• The KIPS Transactions:PartA
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• v.14A no.4
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• pp.203-208
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• 2007

This paper proposes a $64{\times}64$ Modified Booth multiplier using CMOS multi-valued logic circuits. The multiplier based on the radix-4 algorithm is designed with current mode CMOS quaternary logic circuits. Designed multiplier is reduced the transistor count by 64.4% compared with the voltage mode binary multiplier. The multiplier is designed with Samsung $0.35{\mu}m$ standard CMOS process at a 3.3V supply voltage and unit current $5{\mu}m$. The validity and effectiveness are verified through the HSPICE simulation. The voltage mode binary multiplier is achieved the occupied area of $7.5{\times}9.4mm^2$, the maximum propagation delay time of 9.8ns and the average power consumption of 45.2mW. This multiplier is achieved the maximum propagation delay time of 11.9ns and the average power consumption of 49.7mW. The designed multiplier is reduced the occupied area by 42.5% compared with the voltage mode binary multiplier.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.18 no.5
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• pp.1187-1193
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• 2014

This paper presents an effective motion estimation to improve the performance of the motion compensated temporal filtering (MCTF) which is a core part of the wavelet-based scalable video coding. The proposed scheme makes the motion vector field uniform by the modified median operation and the search strategies using adjacent motion vectors, in order to enhance the pixel connectivity which is significantly relevant to the performance of the MCTF. Moreover, the motion estimation with variable block sizes that reflects the features of frames is introduced for further correlation improvement of the motion vector field. Experimental results illustrate that the proposed method reduces the decomposed energy on the temporal high frequency subband frame up to 30.33% in terms of variance compared to the case of the full search with fixed block sizes.

• Journal of the Korea Society of Computer and Information
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• v.28 no.2
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• pp.69-75
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• 2023

Finite field arithmetic operations play an important role in a variety of applications, including modern cryptography and error correction codes. In this paper, we propose an efficient multiplication algorithm over finite fields using the Montgomery multiplication algorithm. Existing multipliers can be implemented using AND and XOR gates, but in order to reduce time and space complexity, we propose an algorithm using NAND and NOR gates. Also, based on the proposed algorithm, an efficient semi-systolic finite field multiplier with low space and low latency is proposed. The proposed multiplier has a lower area-time complexity than the existing multipliers. Compared to existing structures, the proposed multiplier over finite fields reduces space-time complexity by about 71%, 66%, and 33% compared to the multipliers of Chiou et al., Huang et al., and Kim-Jeon. As a result, our multiplier is proper for VLSI and can be successfully implemented as an essential module for various applications.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.35 no.9B
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• pp.1350-1359
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• 2010

Recently many researchers have been proved that general RFID system for proximity authentication is vulnerable to various location-based relay attacks such as distance fraud, mafia fraud and terrorist fraud attacks. The distance-bounding protocol is used to prevent the relay attacks by measuring the round trip time of single challenge-response bit. In 2008, Munilla and Peinado proposed an improved distance-bounding protocol applying void-challenge technique based on Hancke-Kuhn's protocol. Compare with Hancke-Kuhn's protocol, Munilla and Peinado's protocol is more secure because the success probability of an adversary has (5/8)n. However, Munilla and Peinado's protocol is inefficient for low-cost passive RFID tags because it requires large storage space and many hash function computations. Thus, this paper proposes a new RFID distance-bounding protocol for low-cost passive RFID tags that can be reduced the storage space and hash function computations. As a result, the proposed distance-bounding protocol not only can provide both storage space efficiency and computational efficiency, but also can provide strong security against the relay attacks because the adversary's success probability can be reduced by $(5/8)^n$.

• KIPS Transactions on Computer and Communication Systems
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• v.8 no.6
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• pp.127-138
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• 2019

The data response speed is a critical issue of cloud services because it directly related to the user experience. As such, the in-memory database is widely adopted in many cloud-based applications for achieving fast data response. However, the current implementation of the in-memory database is mostly based on the linked list-based hash table which cannot guarantee the constant data response time. Thus, cuckoo hashing was introduced as an alternative solution, however, there is a disadvantage that only half of the allocated memory can be used for storing data. Subsequently, bucketized cuckoo hashing (BCH) improved the performance of cuckoo hashing in terms of memory efficiency but still cannot overcome the limitation that the insert overhead. In this paper, we propose a data management solution called Wall Cuckoo which aims to improve not only the insert performance but also lookup performance of BCH. The key idea of Wall Cuckoo is that separates the data among a bucket according to the different hash function be used. By doing so, the searching range among the bucket is narrowed down, thereby the amount of slot accesses required for the data lookup can be reduced. At the same time, the insert performance will be improved because the insert is following up the operation of the lookup. According to analysis, the expected value of slot access required for our Wall Cuckoo is less than that of BCH. We conducted experiments to show that Wall Cuckoo outperforms the BCH and Sorting Cuckoo in terms of the amount of slot access in lookup and insert operations and in different load factor (i.e., 10%-95%).

• Journal of the Korean Society for Aeronautical & Space Sciences
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• v.42 no.2
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• pp.127-133
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• 2014

This paper proposes a determination method of waypoints to maximize the survivability of a UAV. Voronoi diagram which is used for the initial selection of waypoint candidates is the most widely used path planning technique to avoid the threat as far as possible when the location and strength of the threat are given. But if threat strength is different each other and flight path is constrained along with straight lines, Voronoi diagram has limitations in real applications. In this study, the initial waypoints obtained from Voronoi diagram are optimized considering the shape of each threat. Here, a waypoint is optimized while adjacent waypoints are fixed. By repeating this localized optimization until whole waypoints are converged, computation time for finding the best waypoints is greatly reduced.

• Journal of Korea Multimedia Society
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• v.13 no.7
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• pp.943-949
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• 2010

This paper presents some improvements on VLSI implementation of lifting-based 9/7 wavelet transform by optimization hardware multiplication. The proposed solution requires less logic area and power consumption without performance loss compared to previous wavelet filter structure based on lifting scheme. This paper proposes a better approach to the hardware implementation using Lefevre algorithm based on extensions of Pattern search methods. To compare the proposed structure to the previous solutions on full multiplier blocks, we implemented them using Verilog HDL. For a hardware implementation of the two solutions, the logical synthesis on 0.18 um standard cells technology show that area, maximum delay and power consumption of the proposed architecture can be reduced up to 51%, 43% and 30%, respectively, compared to previous solutions for a 200 MHz target clock frequency. Our evaluation show that when design VLSI chip of lifting-based 9/7 wavelet filter, our solution is better suited for standard-cell application-specific integrated circuits than prior works on complete multiplier blocks.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.49 no.3
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• pp.31-37
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• 2012

This paper presents an efficient hardware architecture to enable the high-speed Givens rotation-based QR decomposition. The proposed architecture achieves a highly parallel givens rotation process by maximizing the number of pivots selected for parallel zero-insertions. Sign-select lookahed (SSL)-CORDIC is also efficiently used for the high-speed givens rotation. The performance of QR decomposition hardware considerably increases compared to the conventional triangular systolic array (TSA) architecture. Moreover, the circuit area of QR decomposition hardware was reduced by decreasing the number of flip-flops for holding the pre-computed results during the decomposition process. The proposed QR decomposition hardware was implemented using TSMC $0.25{\mu}m$ technology. The experimental results show that the proposed architecture achieves up to 70 % speed-up over the TACR/TSA-based architecture for the $8{\times}8$ matrix decomposition.

• Journal of the Korean Institute of Intelligent Systems
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• v.20 no.6
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• pp.761-767
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• 2010

In the case of NAND flash memory, a whole block needs to be erased for update operations because update-in- place operations are not supported in NAND flash memory. Blocks of NAND flash memory have the limited erasure cycles, so frequently updated data (hot data) easily makes blocks worn out. As the result, the capacity of NAND flash memory will be reduced by hot data. In this paper, we propose a wear-leveling algorithm by discriminating hot and cold data based on the update patterns of data. When we applied this scheme to NAND flash memory, we confirmed that the erase counts of blocks became more uniform by mapping hot data to a block with a low erase count and cold data to block with a high erase count.