• Journal of the Institute of Electronics and Information Engineers
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• v.54 no.5
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• pp.24-32
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• 2017

In this paper, a low power 4th order delta-sigma modulator was designed with a high resolution of 12 bits or more for the biological signal processing. Using time-interleaving technique, 4th order delta-sigma modulator was designed with one operational amplifier. So power consumption can be reduced to 1/4 than a conventional structure. To operate stably in the big difference between the two capacitor for kT/C noise and chip size, the variable-stage amplifier was designed. In the first phase and second phase, the operational amplifier is operating in a 2-stage. In the third and fourth phase, the operational amplifier is operating in a 1-stage. This was significantly improved the stability of the modulator because the phase margin exists within 60~90deg. The proposed delta-sigma modulator is designed in a standard $0.18{\mu}m$ CMOS n-well 1 poly 6 Metal technology and dissipates the power of $354{\mu}W$ with supply voltage of 1.8V. The ENOB of 11.8bit and SNDR of 72.8dB at 250Hz input frequency and 256kHz sampling frequency. From measurement results FOM1 is calculated to 49.6pJ/step and FOM2 is calculated to 154.5dB.

• Journal of the Korea Society of Computer and Information
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• v.16 no.10
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• pp.23-31
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• 2011

Recently, Solid state disk is mainly used because this device has lower power consumption as well as higher response time. But it features higher price and lower performance at delete and write operations compared with HDD. To compensate this defect, Hybrid hard disk with internal non-volatile flash memory was issued. This NVCache is used as a kind of cache for disk blocks. In this paper, an I/O scheme for H-HDD is proposed for improving low power consumption as well as response time. Our method is to use this NVCache as read cache mainly and write cache when write requests are concentrated. In read cache operation, disk blocks with higher priority determined on basis of time as well as spatial localities are prefetched, which can improve response time. The write operation is conducted only at write peak time as disk spindle up costs higher battery power as well as response time. Experiments results show that the suggested method can improve response time of H-HDD and lower the power consumption.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.40 no.7
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• pp.518-525
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• 2003

In this paper, we present a fast hardware architecture to implement a parallel 2-dimensional discrete wavelet transform(DWT)based on the lifting scheme DWT framework. The conventional 2-D DWT had a long initial and total latencies to get the final 2D transformed coefficients because the DWT used an entire input data set for the transformation and transformed sequentially The proposed architecture increased the parallel performance at computing the row directional transform using new data splitting method. And, we used the hardware resource sharing architecture for improving the total throughput of 2D DWT. Finally, we proposed a scheduling of hardware resource which is optimized to the proposed hardware architecture and splitting method. Due to the use of the proposed architecture, the parallel computing efficiency is increased. This architecture shows the initial and total latencies are improved by 50% and 66%.

• The KIPS Transactions:PartD
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• v.19D no.2
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• pp.147-150
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• 2012

While LDA is a supervised dimension reduction method which finds projective directions to maximize separability between classes, the performance of LDA is severely degraded when the number of labeled data is small. Recently semi-supervised dimension reduction methods have been proposed which utilize abundant unlabeled data and overcome the shortage of labeled data. However, matrix computation usually used in statistical dimension reduction methods becomes hindrance to make the utilization of a large number of unlabeled data difficult, and moreover too much information from unlabeled data may not so helpful compared to the increase of its processing time. In order to solve these problems, we propose an ensemble approach for semi-supervised dimension reduction. Extensive experimental results in text classification demonstrates the effectiveness of the proposed method.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.16 no.2
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• pp.105-111
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• 2006

Cryptographic application and coding theory require operations in finite field $GF(2^m)$. In such a field, the area and time complexity of implementation estimate by memory and time delay. Therefore, the effort for constructing an efficient multiplier in finite field have been proceeded. Massey-Omura proposed a multiplier that uses normal bases to represent elements $CH(2^m)$ [11] and Agnew at al. suggested a sequential multiplier that is a modification of Massey-Omura's structure for reducing the path delay. Recently, Rayhani-Masoleh and Hasan and S.Kwon at al. suggested a area efficient multipliers for modifying Agnew's structure respectively[2,3]. In [2] Rayhani-Masoleh and Hasan proposed a modified multiplier that has slightly increased a critical path delay from Agnew at al's structure. But, In [3] S.Kwon at al. proposed a modified multiplier that has no loss of a time efficiency from Agnew's structure. In this paper we will propose a multiplier by modifying Rayhani-Masoleh and Hassan's structure and the area-time complexity of the proposed multiplier is exactly same as that of S.Kwon at al's structure for type-II optimal normal basis.

• Proceedings of the Korean Information Science Society Conference
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• 2003.10b
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• pp.4-6
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• 2003

본 논문에서는 대규모 DNA 시퀀스를 위한 트라이 인덱싱 기법을 기반으로 하는 효율적인 부분 시퀀스 검색 기법을 제시한다. 제안된 인덱싱 방안에서는 저장 공간 감소를 위하여 시퀀스의 각 문자를 최소 비트 정보로 표현하며, 저장 구조로서 포인터를 사용하지 않는 디스크 기반의 이진 접미어 트라이 구조를 사용한다. 질의 처리 방안에서는 포인터가 없는 이진 트라이 구조 상에서 질의 시퀀스를 검색하기 위하여 이진 정보 기반의 연산과정을 필요로 하며, 또한 단말 정보를 효율적으로 검색하기 위하여 별도의 단말정보 테이블과 인덱스 구조를 사용한다. 실험 결과에 의하면 제안된 방식은 기존의 접미어 트리 인덱싱 방식에 비하여 약 30~50%의 저장 공간 감소 효과를 가질 뿐 아니라, 평균 질의 처리 시간에 있어 약 20배까지의 성능 개선 효과를 갖는 것으로 나타났다.

• Proceedings of the Korean Information Science Society Conference
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• 2002.10c
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• pp.16-18
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• 2002

다차원 데이터를 온라인으로 분석하기 위해서는 사전에 집계 테이블들을 계산해 둔다. 대용량 고차원 데이터의 경우는 집계 테이블의 분량이 천문학적으로 방대하기 때문에 사전 집계 계산이 현실적으로 불가능한 경우가 많다. 고차원 데이터 처리에 관한 연구로는 데이터의 차원 수를 감소시키거나 인덱스를 압축하여 질의처리 시간을 단축하려는 연구를 들 수 있는데, 이러한 방법들은 고차원 데이터의 온라인 분석시에 발생하는 데이터 폭발 현상을 근본적으로 해결하지는 못한다. 본 연구에서는 고차원 데이터가 분석될 때 실제로 저차원 집계 테이블들이 주로 사용된다는 점에 착안하여 데이터 폭발 현상을 감소시키면서 데이터를 분석하는 방안을 제시한다 이 방법은 사전 집계 연산을 할 때 크기가 방대한 고차원 집계 테이블들의 생성을 생략하고, 3-6차원 또는 그 이하 차원의 집계 테이블들만을 고속으로 동시에 생성하는 방법이다.

• Proceedings of the Korea Institute of Convergence Signal Processing
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• 2000.08a
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• pp.149-152
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• 2000

통신기술의 발달과 정보화 사회로 빠르게 변화되면서, 유선ㆍ무선, 핸즈프리, 원거리 화상회의 등의 다양한 방식의 통신이 이루어지고 있다. 음성통신의 어려운 문제 중에 하나는 주위의 소음이다. 소음은 상황에 따라서 다양하고 복잡하여 그 특성을 분석하기가 어렵다. 소음의 특성과 반향 등을 분석하기 위해서는 수 천 개의 적응필터 탭이 필요하게 된다. 따라서 실시간 소음제거를 위해서는 계산량이 많아 어려움이 따르므로 계산량 감소를 위해 FFT연산에 근거한 주파수 영역의 FDAF 적응필터를 이용하게 되었다. 하지만 계산량은 상당히 감소되었지만, 적응필터의 차수가 증가하면서 시간지연과 하드웨어적으로 복잡하게 되어 블록의 차수를 줄일 수 있는 MDF를 비교 검토하였다.

• Proceedings of the Korea Information Processing Society Conference
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• 2012.04a
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• pp.1131-1133
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• 2012

메모리 가격이 저렴해 짐에 따라 대용량의 데이터베이스 연산이 메모리 안에서 처리될 수 있다. 그에 반해 메모리의 접근속도는 과거에 비해 크게 향상되지 않았기 때문에, 효율적인 캐시 활용이 전체 성능을 결정하는 중요한 요소가 된다. 멀티코어 환경에서 효율적 캐시와 높은 동시성을 모두 만족시키기는 쉽지 않다. 이 논문에서는 알려진 메모리 기반 해시 알고리즘을 비교하고, 각각에 대해 탐색 단계에서 조인 키를 기준으로 정렬 알고리즘을 적용하여 수행 시간과 캐시 미스 감소를 비교한다.

• Journal of the Institute of Electronics and Information Engineers
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• v.49 no.9
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• pp.183-195
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• 2012

We propose a variable-latency Decimal Floating Point(DFP) adder which adopts the dual data path scheme. It is to speed addition and subtraction of operand that has identical exponents. The proposed DFP adder makes use of L. K. Wang's operand alignment algorithm, but operates through high speed data-path in guaranteed accuracy range. Synthesis results show that the area of the proposed DFP adder is increased by 8.26% compared to the L. K. Wang's DFP adder, though critical path delay is reduced by 10.54%. It also operates at 13.65% reduced path than critical path in case of an operation which has two DFP operands with identical exponents. We prove that the proposed DFP adder shows higher efficiency than L. K. Wang's DFP adder when the ratio of identical exponents is larger than 2%.