• Title/Summary/Keyword: 연마 공정

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Fabrication of Silica Nanoparticles by Recycling EMC Waste from Semiconductor Molding Process and Its Application to CMP Slurry (반도체 몰딩 공정에서 발생하는 EMC 폐기물의 재활용을 통한 실리카 나노입자의 제조 및 반도체용 CMP 슬러리로의 응용)

  • Ha-Yeong Kim;Yeon-Ryong Chu;Gyu-Sik Park;Jisu Lim;Chang-Min Yoon
    • Journal of the Korea Organic Resources Recycling Association
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    • v.32 no.1
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    • pp.21-29
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    • 2024
  • In this study, EMC(Epoxy molding compound) waste from the semiconductor molding process is recycled and synthesized into silica nanoparticles, which are then applied as abrasive materials contains CMP(Chemical mechanical polishing) slurry. Specifically, silanol precursor is extracted from EMC waste according to the ultra-sonication method, which provides heat and energy, using ammonia solution as an etchant. By employing as-extracted silanol via a facile sol-gel process, uniform silica nanoparticles(e-SiO2, experimentally synthesized SiO2) with a size of ca. 100nm are successfully synthesized. Through physical and chemical analysis, it was confirmed that e-SiO2 has similar properties compared to commercially available SiO2(c-SiO2, commercially SiO2). For practical CMP applications, CMP slurry is prepared using e-SiO2 as an abrasive and tested by polishing a semiconductor chip. As a result, the scratches that are roughly on the surface of the chip are successfully removed and turned into a smooth surface. Hence, the results present a recycling method of EMC waste into silica nanoparticles and the application to high-quality CMP slurry for the polishing process in semiconductor packaging.

Studies on the AFM analysis of Cu CMP processes for pattern pitch size and density after global planarization (패턴 피치크기 및 밀도에 따른 Cu CMP 공정의 AFM 분석에 관한 연구)

  • 김동일;채연식;윤관기;이일형;조장연;이진구
    • Journal of the Korean Institute of Telematics and Electronics D
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    • v.35D no.9
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    • pp.20-25
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    • 1998
  • Cu removal rates for various SiO$_2$ trench pitch sizes and densities and AFM images of surface profiles after global planarization using Cu CMP technology are investigated. In the experimental results, Cu removal rates are increasing as the pattern densities and pattern pitches are getting high and low, respectively, and then decreasing after local planarization. The rms roughness after global planarization are about 120$\AA$. AFM images with a 50% pattern density for 1${\mu}{\textrm}{m}$ and 2${\mu}{\textrm}{m}$ pitches show that thicknesses of 120~330$\AA$ Cu interconnects have been peeled off and oxide erosion of Cu/Sio$_2$ sidewall is observed. However, AFM images with a 50% pattern density for 10${\mu}{\textrm}{m}$ and 15${\mu}{\textrm}{m}$ pitches show that 260~340$\AA$ thick Cu interconnects have been trenched at the boundaries of Cu/Sio$_2$ sidewall.

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Study On Effect of Fe Density on Electrolyte Exfoliation of Chromium Plating Layer (전해액의 Fe 농도에 의한 크롬도금 탈락 연구)

  • Park, Jin-Saeng
    • Transactions of the Korean Society of Mechanical Engineers A
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    • v.39 no.12
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    • pp.1297-1303
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    • 2015
  • The internal chromium plating of a long-axis tube is widely used in military and industrial application, with the thick hard plating formed using a mixed solution of Chromium acid and catalytic $H_2SO_4$. A large-caliber gun can endure a high explosive force as a result of the increased stiffness and wear resistance provided by this internal hard chromium surface. The internal chromium layer of a tube is prone to exfoliation caused by the high kinetic energy of the projectile and high pressure of the explosion. Therefore, we reviewed the plating process. Chromium plating comprises many steps, including the removal of Grease, water cleaning, electrolytic abrasion, etching, plating, water cleaning, and hydrogen brittleness removal. The exfoliated chromium plating layer is affected by the adhesion property of the plating. In particular, the Fe concentration of the electrolyte affects the adhesion property. The optimum Fe concentration for effectively suppressing the exfoliation of the plating layer was established by using a scanning electron microscope to determine the surface roughness, and the effectiveness was proved in an adhesion test, etc.

A study on the hard surfacing Characteristics of SM45C by using Diode laser (다이오드 레이저를 이용한 SM45C의 표면경화 특성에 관한 연구)

  • Lim, Byung-Chul;Lee, Hong-Sub;Park, Sang-Heup
    • Journal of the Korea Academia-Industrial cooperation Society
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    • v.16 no.3
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    • pp.1620-1625
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    • 2015
  • In this study, a variety of industrial gears, shafts, chains, rollers, mold, etc. are widely used inautomotive steel carbon steel for machine structural SM45C typical material used for the experiments. In order to cure the surface of the test piece after the rough grinding and fine grinding was performed in order polishing. Perform the surface hardening of SM45C lacal area by using a diode laser. The output of the laser diode and the feed rate to the process variable. Micro-hardness testing, microstructure testing, scanning electron microscope testing(SEM), the heat input to the analysis. After analyzing the experiment to compare the mechanical properties of the material. When using a diode laser to assess the soundness of the surface hardening. Accordingly, the process for deriving the optimum demonstrate the feasibility.

Thermal Warpage Behavior of Single-Side Polished Silicon Wafers (단면 연마된 실리콘 웨이퍼의 열에 의한 휨 거동)

  • Kim, Junmo;Gu, Chang-Yeon;Kim, Taek-Soo
    • Journal of the Microelectronics and Packaging Society
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    • v.27 no.3
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    • pp.89-93
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    • 2020
  • Complex warpage behavior of the electronic packages causes internal stress so many kinds of mechanical failure occur such as delamination or crack. Efforts to predict the warpage behavior accurately in order to prevent the decrease in yield have been approached from various aspects. For warpage prediction, silicon is generally treated as a homogeneous material, therefore it is described as showing no warpage behavior due to thermal loading. However, it was reported that warpage is actually caused by residual stress accumulated during grinding and polishing in order to make silicon wafer thinner, which make silicon wafer inhomogeneous through thickness direction. In this paper, warpage behavior of the single-side polished wafer at solder reflow temperature, the highest temperature in packaging processes, was measured using 3D digital image correlation (DIC) method. Mechanism was verified by measuring coefficient of thermal expansion (CTE) of both mirror-polished surface and rough surface.