• Title/Summary/Keyword: 역원

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Design and Analysis of a $AB^2$ Systolic Arrays for Division/Inversion in$GF(2^m)$ ($GF(2^m)$상에서 나눗셈/역원 연산을 위한 $AB^2$ 시스톨릭 어레이 설계 및 분석)

  • 김남연;고대곤;유기영
    • Journal of KIISE:Computer Systems and Theory
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    • v.30 no.1
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    • pp.50-58
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    • 2003
  • Among finite field arithmetic operations, the $AB^2$ operation is known as an efficient basic operation for public key cryptosystems over $GF(2^m)$,Division/Inversion is computed by performing the repetitive AB$^2$ multiplication. This paper presents two new $AB^2$algorithms and their systolic realizations in finite fields $GF(2^m)$.The proposed algorithms are based on the MSB-first scheme using standard basis representation and the proposed systolic architectures for $AB^2$ multiplication have a low hardware complexity and small latency compared to the conventional approaches. Additionally, since the proposed architectures incorporate simplicity, regularity, modularity, and pipelinability, they are well suited to VLSI implementation and can be easily applied to inversion architecture. Furthermore, these architectures will be utilized for the basic architecture of crypto-processor.

Detection of Direction Indicators on Road Surfaces Using Inverse Perspective Mapping and NN (원근투영법과 신경망을 이용한 도로노면 방향지시기호 검출 연구)

  • Kim, Jong Bae
    • KIPS Transactions on Software and Data Engineering
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    • v.4 no.4
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    • pp.201-208
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    • 2015
  • This paper proposes a method for detecting the direction indicator shown in the road surface efficiently from the black box system installed on the vehicle. In the proposed method, the direction indicators are detected by inverse perspective mapping(IPM) and bag of visual features(BOF)-based NN classifier. In order to apply the proposed method to real-time environments, the candidated regions of direction indicator in an image only performs IPM, and BOF-based NN is used for the classification of feature information from direction indicators. The results of applying the proposed method to the road surface direction indicators detection and recognition, the detection accuracy was presented at least about 89%, and the method presents a relatively high detection rate in the various road conditions. Thus it can be seen that the proposed method is applied to safe driving support systems available.

A High-Speed Hardware Design of IDEA Cipher Algorithm by Applying of Fermat′s Theorem (Fermat의 소정리를 응용한 IDEA 암호 알고리즘의 고속 하드웨어 설계)

  • Choi, Young-Min;Kwon, Yong-Jin
    • Journal of KIISE:Computing Practices and Letters
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    • v.7 no.6
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    • pp.696-702
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    • 2001
  • In this paper, we design IDEA cipher algorithm which is cryptographically superior to DES. To improve the encryption throughput, we propose an efficient design methodology for high-speed implementation of multiplicative inverse modulo $2^{15}$+1 which requires the most computing powers in IDEA. The efficient hardware architecture for the multiplicative inverse in derived from applying of Fermat's Theorem. The computing powers for multiplicative inverse in our proposal is a decrease 50% compared with the existing method based on Extended Euclid Algorithm. We implement IDEA by applying a single iterative round method and our proposal for multiplicative inverse. With a system clock frequency 20MGz, the designed hardware permits a data conversion rate of more than 116 Mbit/s. This result show that the designed device operates about 2 times than the result of the paper by H. Bonnenberg et al. From a speed point of view, out proposal for multiplicative inverse is proved to be efficient.

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Scalable multiplier and inversion unit on normal basis for ECC operation (ECC 연산을 위한 가변 연산 구조를 갖는 정규기저 곱셈기와 역원기)

  • 이찬호;이종호
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.40 no.12
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    • pp.80-86
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    • 2003
  • Elliptic curve cryptosystem(ECC) offers the highest security per bit among the known publick key system. The benefit of smaller key size makes ECC particularly attractive for embedded applications since its implementation requires less memory and processing power. In this paper, we propose a new multiplier structure with configurable output sizes and operation cycles. The number of output bits can be freely chosen in the new architecture with the performance-area trade-off depending on the application. Using the architecture, a 193-bit normal basis multiplier and inversion unit are designed in GF(2$^{m}$ ). It is implemented using HDL and 0.35${\mu}{\textrm}{m}$ CMOS technology and the operation is verified by simulation.