• Journal of the Korean Vacuum Society
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• v.16 no.3
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• pp.197-204
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• 2007

Ultra thin Er-silicide layers formed by Er deposition on the clean p-silicon and in situ post annealing technique were investigated with respect to change of the Schottky barrier height. The formation of Er silicides was confirmed by XPS results. UPS measurements revealed that the workfunction of the silicide decreased and was saturated as the deposited Er thickness increased up to $10{\AA}$. We found that the silicides were mainly composed of Er5Si3 phase through the XRD experiments. After Schottky diodes were fabricated with the Er silicide/p-Si junctions, the Schottky barrier heights were calculated $0.44{\sim}0.78eV$ from the I-V measurements of the Schottky diodes. There was large discrepancy in the Schottky barrier heights deduced from the UPS with the ideal junction condition and the real I-V measurements, so that we attributed the discrepancy to the $Er_5Si_3$ phase in the Er-silicides and the large interfacial density of trap state of it.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2007.11a
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• pp.75-76
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• 2007

Poly-Si Schottky barrier Thin Film Transistor (SB-TFT) is manufactured with erbium silicided source/drain. High quality poly-Si film was obtained by crystallizing the amorphous Si film with Excimer laser annealing (ELA) method. The fabricated poly-Si SB-TFT devices showed low leakage current and large on/off current ratio. Moreover, the electrical characteristics were considerably improved by 3% $H_2/N_2$ gas annealing, which is attributed to the reduction of trap states at the grain boundaries and interface trap states at gate oxide/poly-si channel.

• Journal of the Korean Vacuum Society
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• v.18 no.4
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• pp.302-309
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• 2009

We fabricated a Si nano floating gate memory with Schottky barrier tunneling transistor structure. The device was consisted of Schottky barriers of Er-silicide at source/drain and Si nanoclusters in the gate stack formed by LPCVD-digital gas feeding method. Transistor operations due to the Schottky barrier tunneling were observed under small gate bias < 2V. The nonvolatile memory properties were investigated by measuring the threshold voltage shift along the gate bias voltage and time. We obtained the 10/50 mseconds for write/erase times and the memory window of $\sim5V$ under ${\pm}20\;V$ write/erase voltages. However, the memory window decreased to 0.4V after 104seconds, which was attributed to the Er-related defects in the tunneling oxide layer. Good write/erase endurance was maintained until $10^3$ write/erase times. However, the threshold voltages moved upward, and the memory window became small after more write/erase operations. Defects in the LPCVD control oxide were discussed for the endurance results. The experimental results point to the possibility of a Si nano floating gate memory with Schottky barrier tunneling transistor structure for Si nanoscale nonvolatile memory device.