• Korean Journal of Optics and Photonics
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• v.21 no.2
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• pp.41-45
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• 2010

In order to obtain thinner and brighter backlight units (BLU), we simulated a new-type backlight unit. A micro-lens array sheet was formed on the upper plane of the light guide plate (LGP) comprising the backlight unit. Also, in order to match with the LGP, we simulated a functional optical sheet. The conventional BLU uses one LGP and four optical sheets, but we simulated a BLU that uses one optical sheet. Simulation results have revealed that our BLU can achieve the same luminance and 30% better view angle as compared with conventional ones.

• Journal of the Korea Society of Computer and Information
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• v.6 no.3
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• pp.84-90
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• 2001

The development of network and the other communication-network can generate serious problems. So, it is highly required to control security of network. These problems related secu be developed and keep up to confront with anti-security part such as hacking, cracking. Th way to preserve security from hacker or cracker without developing new cryptographic algori keeping the state of anti-cryptanalysis in a prescribed time by means of extending key-length In this paper, the proposed montgomery multiplication structured unit array method in carry generated part and variable length multiplicator for eliminating bottle neck effect with the RSA cryptosystem. Therefore, this proposed montgomery multiplicator enforce the real time processing and prevent outer cracking.

• Journal of IKEEE
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• v.22 no.4
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• pp.1093-1098
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• 2018

In this paper, we proposed a methodology for portable disease diagnosis platform using high performance computing. The proposed methodology consists of gathering clinical data, diagnosis and feature selection algorithm, implementation of diagnosis platform. For the algorithm verification, a clinical data which is obtained from 401 people(314 normal subjects and 87 liver cancer patients) using a microarray consists of 1,146 aptamers were used. As the result, we could diagnosis liver cancer with 97.5% accuracy using the 32 selected aptamers. Based on these results, we designed and implemented a portable disease diagnosis platform which has 32 bio-signals as inputs.

• Korean Journal of Optics and Photonics
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• v.33 no.6
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• pp.267-274
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• 2022

In this paper, we report the design and fabrication of binary diffractive optical elements (DOEs) for random-dot-pattern projection for Schlieren imaging. We selected the binary phase level and a pitch of 10 ㎛ for the DOE, based on cost effectiveness and ease of manufacture. We designed the binary DOE using an iterative Fourier-transform algorithm with binary phase optimization. During initial optimization, we applied a computer-generated pseudorandom dot pattern of uniform intensity as a target pattern, and found significant intensity nonuniformity across the field. Based on the evaluation of the initial optimization, we weighted the target random dot pattern with Gaussian profiles to improve the intensity uniformity, resulting in the improvement of uniformity from 52.7% to 90.8%. We verified the design performance by fabricating the designed binary DOE and a beam projector, to which the same was applied. The verification confirmed that the projector produced over 10,000 random dot patterns over 430 mm × 430 mm at a distance of 5 meters, as designed, but had a slightly less uniformity of 84.5%. The fabrication errors of the DOE, mainly edge blurring and spacing errors, were strong possibilities for the difference.

• Journal of KIISE:Computer Systems and Theory
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• v.32 no.4
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• pp.160-167
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• 2005

Among finite filed arithmetic operations, division/inverse is known as a basic operation for public-key cryptosystems over $GF(2^{m})$ and it is computed by performing the repetitive $AB^{2}$ multiplication. This paper presents a digit-serial-in-serial-out systolic architecture for performing the $AB^2$ operation in GF$(2^{m})$. To obtain L×L digit-serial-in-serial-out architecture, new $AB^{2}$ algorithm is proposed and partitioning, index transformation and merging the cell of the architecture, which is derived from the algorithm, are proposed. Based on the area-time product, when the digit-size of digit-serial architecture, L, is selected to be less than about m, the proposed digit-serial architecture is efficient than bit-parallel architecture, and L is selected to be less than about $(1/5)log_{2}(m+1)$, the proposed is efficient than bit-serial. In addition, the area-time product complexity of pipelined digit-serial $AB^{2}$ systolic architecture is approximately $10.9\%$ lower than that of nonpipelined one, when it is assumed that m=160 and L=8. Additionally, since the proposed architecture can be utilized for the basic architecture of crypto-processor and it is well suited to VLSI implementation because of its simplicity, regularity and pipelinability.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.38 no.5
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• pp.509-517
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• 2001

Full-search algorithm requires large amount of computation which causes time delay or very complex hardware architecture for real time implementation. In this paper, we propose a fast motion estimator based on bit-plane matching, which reduce the computational complexity and the hardware cost. In the proposed motion estimator, the conventional motion estimation algorithms are applied to the binary images directly extracted from the video sequence. Furthermore, in the proposed VLSI motion estimator, we employ a Pair of processing cores that calculate the motion vector continuously By controlling the data flow in a systolic fashion using the internal shift registers in the processing cores, we avoid using SRAM (local memory) so that we remove the time overhead for accessing the local memory and adopt lower-cost fabrication technology. We modeled and tested the proposed motion estimator in VHDL, and then synthesized the whole system which has been integrated in a 0.6-$\mu$m triple-metal CMOS chip of size 8.15 X 10.84$\textrm{mm}^2$.

• The Journal of the Korea institute of electronic communication sciences
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• v.10 no.5
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• pp.549-556
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• 2015

In this paper, design and fabrication for inset fed microstrip patch antennas applied to the $3{\times}3$ array CSLR and eight CSLR, respectively, to the ground plane are studied. The theoretical results are compared to the experimental results for the return loss and radiation pattern. For 'CSLR 09' antenna, the theoretical result for the resonant frequency and the return loss are 2.82 GHz and - 25.35 dB, respectively. The experimental results are obtained for a 2.885 GHz, -30.72 dB. Theoretical results for the resonant frequency and the return loss of the 'CSLR 08' antenna are 2.82 GHz, -16.77 dB, respectively, and the experimental results are obtained for a 2.885 GHz, -14.90 dB. In addition, E-plane and H-plane radiation patterns in comparison with designed and fabricated antennas are in good agreement.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.36C no.6
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• pp.18-26
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• 1999

This paper presents the architecture and design of a DSSS MODEM ASIC chip for wireless local area networks (WLAN). The implemented MODEM chip supports the DSSS physical layer specifications of the IEEE 802.11. The chip consits of a transmitter and a receiver which contain a CRC encoder/decoder, a differential encoder/decoder, a frequency offset compensator and a timing recovery circuit. The chip supports various data rates, i.e., 4,2 and 1Mbps and provides both DBPSK and DQPSK for data modulation. We have performed logic synthesis using the $SAMSUNG^{TM}$ $0.6{\mu}m$ gate array library and the implemented chip consists of 53,355 gates. The MODEM chip operates at 44MHz, the package type is 100-pin QFP and the power consumption is 1.2watt at 44MHz. The implemented MODEM architecture shows lower BER compared with the Harris HSP3824.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.18 no.5
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• pp.63-68
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• 2018

In this paper, We intended to design various things for the realization of SoS(System on Substrate) with SIW in 24GHz ISM 밴드(24-24.25GHz). As part of them, We integrated SIW, transition and MPAA as SoS on the same substrate and investigated its characteristics. We used Rogers Ro4350 with relative permittivity of 3.48 and thickness of 20mil. As results of optimal design, insertion loss of the SIW with 11.55mm length showed 0.32dB and insertion loss of 0.19dB occurred in transition to $50{\Omega}$ microstrip. Characteristics of the MPAA integrated on the same substrate as SoS are very similar to those of stand-alone MPAA. But the integrated MPAA decreased by 0.58dB in gain, which is the sum of SIW insertion loss and transition insertion loss, and by 0.7dB in SLL compared that of stand-alone MPAA. However, the bandwidth was increased by 19.4% as it changed from 670MHz to 800Mhz.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.4
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• pp.26-33
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• 2010

This paper presents a multi-channel capacitive touch sensing unit for SoC applications. This unit includes a simple common processing unit and switch array to detect the touch sensing input by capacitive-time(C-T) conversion method. This touch sensor ASIC is designed based on the Capacitive-Time(C-T) conversion method to have advantages of small current and chip area, and the minimum resolution of the unit is 41 fF per count with the built-in sensing oscillator, LDO regulator and $I^2C$ for no additional external components. This unit is implemented in 0.18 um CMOS process with dual supply voltage of 1.8 V and 3.3 V. The total power consumption of the unit is 60 uA and the area is 0.26 $mm^2$.