• Title/Summary/Keyword: 어레이 설계

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Design of array typed inkjet head for line-printing (라인 프린팅을 위한 어레이 방식 잉크젯 헤드 설계)

  • Sang-Hyun Kim
    • The Journal of the Convergence on Culture Technology
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    • v.9 no.5
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    • pp.529-534
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    • 2023
  • Although line printing technology is capable of high-speed and large area printing, residual stresses generated during the manufacturing process can deform the feedhole, causing nozzle plate crack or ink leaks. Therefore, in this paper, we propose a new thermal inkjet print head that is robust, reliable and more suitable for line-printing. The amount of deformation of the conventional line printing head measured through the experiment was converted into an equivalent load, and the validity of the load estimation method was verified through FEA analysis. In addition, in order to minimize deformation without increasing the head size, the head structure was designed to increase internal rigidity by reinforcing the unit nozzle with a pillar or support wall or by adding a support beam or dry/wet etched bridge. The FEA analysis results show that the feedhole deformation was reduced by up to 90%, and it is confirmed that the suggested print head with dry etched feedhole bridge operates normally without nozzle plate cracks and ink leakage through fabrication.

A Study on the design of two's complement bit-serial FIR filter with systolic array architecture (Systolic Array를 이용한 Two's Complement Bit-Serial Fir 필터 설계에 관한 연구)

  • 엄두섭;박노경;차균현
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.14 no.5
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    • pp.442-452
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    • 1989
  • This Paper describes the impleentation of two's complement bit-serial FIR filter with systolic architectur. The filter coefficients are represented as sign and magnitude form and the input data is represented as two's complement form. We use systolic array to obtain high operation speed so this FIR filter sucessfully operates in real-time environment.

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Design of Thin Frequency Selective Surface Superstrates for Dual-Band Directivity Enhancement (이중 대역 지향성 증가용 박판 주파수 선택적 표면의 설계)

  • Lee Dong-Hyun;Lee Young-Ju;Yeo Jun-Ho;Mittra Raj;Park Wee-Sang
    • The Journal of Korean Institute of Electromagnetic Engineering and Science
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    • v.17 no.7 s.110
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    • pp.648-658
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    • 2006
  • We propose a thin frequency selective surface(FSS) superstrate etched on a substrate for dual-band directivity enhancement, and present a design method of the superstrate. In the proposed new design, two FSS arrays with the same periodicity, but with different alignments are placed above and below a thin dielectric layer to overcome the problem of conventional superstrates for dual band directivity enhancements. Based on the unit-cell simulation, several important parameters that characterize the thin FSS superstrate are investigated, and the procedure for designing such a superstrate is described. We compare the resonant frequencies and the qualify factors of the unit cell with those of three FSS antenna composites with different quality factors, and identify the quality factors which support similar directivity enhancement at the dual-band directivity enhancement. It was found that there is an optimum FSS array size of a superstrate to enhance the directivity most efficiently. Measured results for a fabricated superstrate show a good agreement with the simulated ones.

Deign of Small-Area Differential Paired eFuse OTP Memory for Power ICs (Power IC용 저면적 Differential Paired eFuse OTP 메모리 설계)

  • Park, Heon;Lee, Seung-Hoon;Jin, Kyo-Hong;Ha, Pan-Bong;Kim, Young-Hee
    • The Journal of Korea Institute of Information, Electronics, and Communication Technology
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    • v.8 no.2
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    • pp.107-115
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    • 2015
  • In this paper, a small-area 32-bit differential paired eFuse OTP memory for power ICs is designed. In case of smaller number of rows than that of columns for the OTP memory cell array, a scheme for the cell array reducing the number of SL driver circuits requiring their larger layout areas by routing the SL (source line) lines supplying programming currents for eFuse links in the row direction instead of the column direction as well as a core circuit is proposed. In addition, to solve a failure of being blown for non-blown eFuse links by the electro-migration phenomenon, a regulated voltage of V2V ($=2V{\pm}0.2V$) is used to a RWL (read word line) driver circuit and a BL (bit line) pull-up driver circuit. The layout size of the designed 32-bit eFuse OTP memory is $228.525{\mu}m{\times}105.435{\mu}m$, which is confirmed to be 20.7% smaller than that of the counterpart using the conventional cell array routing, namely $197.485{\mu}m{\times}153.715{\mu}m$.

Platform Design for Multiple Sensor Array Signal Verification (다중 센서 어레이 신호 검증을 위한 플랫폼 설계)

  • Park, Jong-Sik;Lee, Seong-Soo
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.15 no.11
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    • pp.2480-2487
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    • 2011
  • As sensor technology grows up in fields such as environmental hazards detecting system, ubiquitous sensor network, intelligent robot, the sensing and detecting system for sensor is increasing. The sensor data is measured by change of chemical and physical status. Because of decrepit sensor or various sensing environment, it is problem that sensor data is inaccurate result. So the reliability of sensor data is essential. In this paper, we proposes a reliable sensor signal processing platform for various sensor. To improve reliability, we use same sensors in multiple array structure. As sensor data is corrected by spatial and temporal relation signal processing algorithm for measured sensor data, reliability of sensor data can be improved. The exclusive protocol between platform components is designed in order to verify sensor data and sensor state in various environment.

Implementation of Cushion Type Posture Discrimination System Using FSR Sensor Array (FSR 센서 어레이를 이용한 방석형 자세 판별시스템의 구현)

  • Kim, Mi-Seong;Seo, Ji-Yun;Noh, Yun-Hong;Jeong, Do-Un
    • Journal of the Institute of Convergence Signal Processing
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    • v.20 no.2
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    • pp.99-104
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    • 2019
  • Recently, modern people are increasing the incidence of various musculoskeletal diseases due to wrong posture. Prevention is possible through proper posture habit, but it is not easy to recognize posture by oneself. Various studies have been conducted to monitor persistent posture in daily life, but most studies using constrained measurement methods and high-cost measurement equipment are not suitable for daily life. In this paper, we implemented a posture discrimination system using a FSR sensor array that can induce posture correction spontaneously through sitting posture monitoring in daily life. The implemented system is designed as a cushion type so it is easy to apply to existing chair. In addition, it can identify five most common postures in everyday life, and can monitor real-time through Android-based smart-phone monitoring application. For the performance evaluation of the implemented system, each posture was measured 50 times repeatedly. As a result, 97.6% accuracy was confirmed.

A Study on Arrangement and Configuration of Acoustic Output Equipment according to Type of Church Broadcast Sources (교회 방송음원의 종류에 따른 음향출력 설비 구성 배치에 관한 연구)

  • Park, Eunjin;Lee, Seonhee
    • Journal of Satellite, Information and Communications
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    • v.11 no.3
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    • pp.80-85
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    • 2016
  • In this paper, by comparatively analyzing horn type speaker and line array type speaker developed based on line sound source theory and point sound source theory, we research whether theory is adaptable or not in real. Academically, point sound source is attenuated as much as 6dB in accordance with double distance and line sound source is attenuated as much as 3dB in accordance with double distance. Line array speaker system developed based on line sound source is analyzed by theory of line sound source about occurring small sound pressure attenuation and it is propose of research that array composition of right speaker is selected in accordance with use purpose and environment. For this purpose, we analyze theory of point sound source and line sound source. we analyze parameter value by simulating designed horn type speaker and line array speaker based on theory.

Design of an Analog Array Using Floating Gate MOSFETs (부유게이트를 이용한 아날로그 어레이 설계)

  • 채용웅;박재희
    • Journal of the Korean Institute of Telematics and Electronics C
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    • v.35C no.10
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    • pp.30-37
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    • 1998
  • An analog array with a 1.2 $\mu\textrm{m}$ double poly floating gate transistor has been developed with a standard CMOS fabrication process. The programming of each cell by means of an efficient control circuit eliminates the unnecessary erasing operation which has been widely used in conventional analog memories. It is seen that the path of the signal for both the programming and the reading is almost exactly the same since just one comparator supports both operations. It helps to eliminate the effects of the amplifier input-offset voltage problem on the output voltage for the read operation. In the array, there is no pass transistor isolating a cell of interest from the adjacent cells in the array. Instead of the extra transistors, one extra bias voltage, Vmid, is employed. The experimental results from the memory shows that the resolution of the memory is equivalent to the information content of at least six digital cells. Programming/erasing of each cell is achieved with no detectable disturbance of adjacent cells. Finally, the unique shape of the injector structure in a EEPROM is adopted as a cell of analog array. It reduces the programming voltage below the transistor breakdown voltage without any special fabrication process.

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Design of an Efficient VLSI Architecture of SADCT Based on Systolic Array (시스톨릭 어레이에 기반한 SADCT의 효율적 VLSl 구조설계)

  • Gang, Tae-Jun;Jeong, Ui-Yun;Gwon, Sun-Gyu;Ha, Yeong-Ho
    • Journal of the Institute of Electronics Engineers of Korea SP
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    • v.38 no.3
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    • pp.282-291
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    • 2001
  • In this paper, an efficient VLSI architecture of Shape Adaptive Discrete Cosine Transform(SADCT) based on systolic array is proposed. Since transform size in SADCT is varied according to the shape of object in each block, it are dropped that both usability of processing elements(PE´s) and throughput rate in time-recursive SADCT structure. To overcome these disadvantages, it is proposed that the architecture based on a systolic way structure which doesn´t need memory. In the proposed architecture, throughput rate is improved by consecutive processing of one-dimensional SADCT without memory and PE´s in the first column are connected to that in the last one for improvement of usability of PE. And input data are put into each column of PE in parallel according to the maximum data number in each rearranged block. The proposed architecture is described by VHDL. Also, its function is evaluated by MentorTM. Even though the hardware complexity is somewhat increased, the throughput rate is improved about twofold.

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Numerical Analysis of Ultrasonic Beam Profile Due to the Change of the Number of Piezoelectric Elements for Phased Array Transducer (Phased Array트랜스듀서에 있어서 구성 압전소자수의 변화에 따른 초음파 빔 전파 특성의 수치 해석)

  • Choi, Sang-Woo;Lee, Joon-Hyun
    • Journal of the Korean Society for Nondestructive Testing
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    • v.19 no.3
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    • pp.207-216
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    • 1999
  • A phased array is a multi-element piezoelectric device whose elements are individually excited by electric pulses at programmed delay time. One of the advantages of using phased array in nondestructive evaluation (NDE) application over conventional ultrasonic transducers is their great maneuverability of ultrasonic beam. There are some parameters such as the number and the size of the piezoelectric elements and the inter-element spacing of the elements to design phased array transducer. In this study, the characteristic of ultrasonic beam for phased array transducer due to the variation of the number of elements has been simulated for ultrasonic SH-wave on the basis of Huygen's principle. Ultrasonic beam directivity and focusing due to the change of time delay of each element were discussed due to the change of the number of piezoelectric elements. It was found that ultrasonic beam was much more spreaded and hence its sound pressure was decreased as steering angle of ultrasonic beam was increased. In addition, the ability of ultrasonic bean focusing decreased gradually with the increase of focal length at the same piezoelectric elements. However, the ability of beam focusing was improved as the number of consisting elements was increased.

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