• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.2
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• pp.86-94
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• 2007

The NoC (network-on-chip) approach is a promising solution to the increasing complexity of on-chip communication problems because of its high scalability. But, NoC applications generally consume a lot of power, because they require a large design space to accommodate many parallel IPs and network communication channels. It is not easy to analyze the power consumption of NoC applications with conventional simulation methods using simple power models. In addition, there are also many limitations in using sophisticated simulation models because they require long execution time and large efforts. In this paper, we apply a cycle-accurate energy measurement technique and tool to the FPGA prototypes, which are generally used to verify the correctness of SoC designs, as a practical indication of the power consumption of real NoC applications. An NoC-based JPEG encoder implementation is used as a case study to demonstrate the effectiveness of our approach.

• Journal of the Institute of Convergence Signal Processing
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• v.4 no.3
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• pp.7-14
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• 2003

MPEG-1 audio standard is the algorithm for the compression of high-qualify digital audio signals. The standard dictates the functions of encoder and decoder pair, and includes three different layers as the complexity and the performance of the encoder and decoder. In this paper, we implemented the real-time system of MPEG-1 audio layer III decoder(MP3) with the TMS320C541 fixed point DSP chip. MP3 algorithm uses psycho-acoustic characteristic of human hearing system, and it reduces the amount of data with eliminating the signals hard to be heard to the hearing system of human being. It is difficult to implement MP3 decoder with fixed Point DSP because of it's broad dynamic range. We implemented realtime system with fixed DSP chip by using weighted look-up tables to reduce the amount of calculation and solve the problem of broad dynamic range.

• Journal of the Korean Recycled Construction Resources Institute
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• v.10 no.3
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• pp.321-326
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• 2022

In this study, cogeneration power plants that use biomass as a raw material to convert them into energy have recently received a lot of attention worldwide and are gradually increasing in South Korea. Therefore, in order to confirm the possibility of using the generated floor material as a fine aggregate for concrete, properties and stability evaluation experiments were performed. Compared to standard sand, the compressive strength of wood chip aggregate was improved by 11 % to 111 %, the length change rate was 89 %, and the waste processing test results met all criteria for hazardous substances. All of these are satisfied, and it is judged that the floor materials by the cogeneration power plant can be used as a fine aggregate for concrete.

• Geotechnical Engineering
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• v.7 no.3
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• pp.51-64
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• 1991

The reliable estimation of pile bearing capacity is essential for the improvement of the re- liability and the cost-effectiveness of the design. There have been numerous pile bearing capacity prediction methods proposed up to now, however, execpt for the estimation made from the result of the pile loading test, not one method is appropriate for the reliable prediction. Due to the considerable time and expenses required to carry out the pile loading test, the test has seldom been utilized. The development of Simple Pile Loading Test(SPLT) which utilizes the pile skin friction as the required reaction force to cause the pile tip settlement, provides a solution to perform more pile loading tests and consequently a more economical pile design is possible. The separate measurement of skin friction and tip resistance during the course of performing SPLT provides a better understanding of the pile behavior than the result of the conventional pile loading test where only the total resistance is measured. On the other hand, there are some points to be clarified in order to apply the test results of SPLT to practical problem. They are the direction of the applied load to mobilize the skin friction and the use of reduced sized sliding core. In this research, both the SPLT and the conventional pile loading test on 406mm diameter steel pipe pile have been performed. From the result, it would be safe to use the measured SPLT skin friction value directly in the design, since the value is somewhat lower than the value measured in the conventional test. It is further assumed that the tip resistance value of the reduced sized sliding core should properly be analysed by taking the incluonce of scale effect into consideration.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.36C no.12
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• pp.11-19
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• 1999

Fractal image compression algorithm has been studied mostly not in the view of hardware but software. However, a general processor by software can't decode fractal compressed images in real-time. Therefore, it is necessary that we develop a fast dedicated hardware. However, design examples of dedicated hardware are very rare. In this paper, we designed a quadtree fractal-based compressed image decoder which can decode $256{\times}256$ gray-scale images in real-time and used two power-down methods. The first is a hardware-optimized simple post-processing, whose role is to remove block effect appeared after reconstruction, and which is easier to be implemented in hardware than non-2' exponents weighted average method used in conventional software implementation, lessens costs, and accelerates post-processing speed by about 69%. Therefore, we can expect that the method dissipates low power and low energy. The second is to design a power dissipation in the multiplier can be reduced by about 28% with respect to a general array multiplier which is known efficient for low power design in the size of 8 bits or smaller. Using the above two power-down methods, we designed decoder's core block in 3.3V, 1 poly 3 metal, $0.6{\mu}m$ CMOS technology.

• Journal of the Microelectronics and Packaging Society
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• v.14 no.3
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• pp.21-27
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• 2007

Nickel bumps for ACF(anisotropic conductive film) flip chip application were fabricated by electroless and electro plating and their mechanical properties and impact reliability were examined through the compressive test, bump shear test and drop test. Stress-displacement curves were obtained from the load-displacement data in the compressive test using nano-indenter. Electroplated nickel bumps showed much lower elastic stress limits (70MPa) and elastic moduli ($7.8{\times}10^{-4}MPa/nm$) than electroless plated nickel bumps ($600-800MPa,\;9.7{\times}10^{-3}MPa/nm$). In the bump shear test, the electroless plated nickel bumps were deformed little by the test blade and bounded off from the pad at a low shear load, whereas the electroplated nickel bumps allowed large amount of plastic deformation and higher shear load. Both electroless and electro plated nickel bumps bonded by ACF flip chip method showed high impact reliability in the drop impact test.

• Journal of the Korean Institute of Telematics and Electronics S
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• v.36S no.12
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• pp.67-75
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• 1999

In this paper, we present an ASIC(Application Specific Integrated Circuit) design of wavelet transform filter Wavelet transform is used in lots of application fields which include image compression, because it has an excellent energy compaction. The operation characteristic and performance of wavelet transform filter are analyzed by using verilog-HDL(Hardware Description Language). In this paper, the designed wavelet transform filter uses line memory to improve data processing rate. Generally, when it reads and writes data of DRAM by using Fast Page Mode, input and output processing is very fast in horizontal direction but substantially slow in vertical direction. The use of line memory solves this low speed processing problem. As a result, though the size of the chip is getting larger, processing time for an image frame becomes 4.66ms. Generally, since the limit of 1 frame processing time on the data of TV video is 33ms, so it is appropriate for TV video.

• Korean Chemical Engineering Research
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• v.49 no.1
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• pp.120-127
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• 2011

For the development of the environment-friendly insulating composite materials, natural cellulose (wood chip and sawdust) was used as a core material and activated Hwangtoh was used as a binder. Various specimens were prepared with the water/binder ratio and natural cellulose/binder ratio. The physical properties of these specimens were then investigated through compressive and flexural strength test, absorption test, hot water resistance test, thermal conductivity, measurement of pore distribution and observation of micro-structures using scanning electron microscope (SEM). Results showed that the absorption ratio increased with the increase of natural cellulose/binder ratio but decreased remarkably with the increase of polymer/binder ratio. The compressive and flexural strength development varied appreciably with the increase of water/binder ratio and natural cellulose/binder ratio. On the other hand, thermal conductivity decreased with the increase of natural cellulose/binder ratio and polymer/binder ratio. Through SEM, it was found that activated Hwangtoh that reacted with water formed a hydrate crystal leading to the compact structure and the total pore volume of the specimen using activated Hwangtoh was smaller than that of the non-activated Hwangtoh.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.46 no.5
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• pp.151-161
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• 2009

Audio Video Standard (AVS) is the audio and video compression standard that was developed for domestic video applications in China. AVS employs low complexity tools to minimize degradation of RD performance of the state-the-art video codec, H.264/AVC. The AVS video codec consists of $8{\times}8$ block prediction and the same size transform to improve compression efficiency for VGA and higher resolution sequences. Currently, the AVS has been adopted more and more for IPTV services and mobile applications in China. So, many consumer electronics companies and multimedia-related laboratories have been developing applications and chips for the AVS. In this paper, we implemented the AVS video decoder and optimize it on TI's Davinci EVM DSP board. For improving the decoding speed and clocks, we removed unnecessary memory operations and we also used high-speed VLD algorithm, linear assembly, intrinsic functions and so forth. Test results show that decoding speed of the optimized decoder is $5{\sim}7$ times faster than that of the reference software (RM 5.2J).

• The Journal of the Acoustical Society of Korea
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• v.24 no.7
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• pp.387-394
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• 2005

In this paper, we propose a new transmission technique of audio signals for the serial connection of the speakers of multiple-channel audio systems. Analog audio signals from a multi-channel audio system are converted into digital signals with signal processing steps and transferred to each speaker through a serial line. The signal processing steps contain data compression and packet generation in association with audio signal characteristics. Each speaker gets its corresponding digital audio signals from the transmitted packets and converts the signals into analog audio signals to make sounds with the speaker All the proposed functions in this paper are modeled in VHDL. implemented with FPGA chips, and tested for actual multi-channel audio systems.