• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.16 no.8
• /
• pp.1753-1758
• /
• 2012

This paper introduces analog FIR filters based on a distributed amplifier and analyzes the proposed filter's characteristics. A simple design method of an analog FIR filter based on the digital filter design technique is also introduced. The proposed analog FIR filters are a moving average(MA) and a comb type filters with no multiplier. This simple structures of the proposed filters may enable to operate at multi-GHz frequency range and applicable to combine a filter and an amplifier of RF system. The proposed analog FIR filters were implemented with standard $0.18{\mu}m$ CMOS technology. The designed GHz analog FIR filters are simulated by Cadence Spectre and compared to the results of digital FIR filters obtained from MATLAB simulations. From the simulation results, the characteristics of the proposed analog FIR filters are fairly well matched with those of digital FIR filters.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
• /
• v.20 no.10
• /
• pp.35-40
• /
• 2006

In this paper, a current-mode analog variable finite-impulse-response (FIR) filter with variable tap coefficient circuits is proposed for frequency selective wireless personal area network(WPAN) system or terminals. From the circuit simulation the operation of the 7-tap FIR filter is confirmed. The 0.0625-step tap coefficient circuit is designed and fabricated with $0.8[{\mu}m]$ CMOS technology. The proposed FIR filter has a variable length of taps and variable coefficients, so it has a potential for being used to frequency selective WPAN system or frequency selective wireless communication terminals.

• The Journal of the Convergence on Culture Technology
• /
• v.6 no.3
• /
• pp.427-430
• /
• 2020

The multi-channel analog signal to digital signal conversion is increasing in the field of IoT and medical measurement equipments. It has chip area and power consumption constraints to use a few single or 2_channel ADC for multi_channel application. This paper described to design and implement a proposed comb filter for multi-channel, 24bit ADC. The function of proposed comb filter is verified by matlab simulation and the FPGA test board. It was fabricated using SK Hynix 0.35㎛ CMOS standard process. The performance and chip size is compared with the existing design method that uses integrator/differentiator and FIR construction. The proposed comb filter is expected to use the IoT product and medical measurement equipments that require multi-channel, low power consumption and small hardware size.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
• /
• 2007.06a
• /
• pp.758-761
• /
• 2007

Digital signal processing technique is applied in wide fields such as speech processing, image processing and spectrum analysis. Therefore, in order to do frequency selective operation digital filter is used in stead of analog filter and sharp filter characteristics can be implemented. Since finite impulse response (FIR) digital filter as nonrecursive type represents linear phase response characteristics and is always stable and is used in fields regarding wave information importantly such as data transmission. And due to frequency characteristics, in order to remove the Gibbs phenomenon generating around a discontinuous point, filter is designed through window function method. Therefore, in this paper to improve performance of FIR digital filter, a modified window function was applied. And the proposed method was compared with conventional methods using peak side-lobe and transition properties in simulations.

• Proceedings of the Korea Institutes of Information Security and Cryptology Conference
• /
• 1992.11a
• /
• pp.55-70
• /
• 1992

기존의 음성 정보 보호 방식의 단점인 비화의 감소, 키 수의 제한, 상관 관계를 이용한 제3자의 해독 둥의 문제점을 해결할 수 있는 호핑 필터를 이용한 이차원 진폭 스크램블링은 현대 아날로그 음성 신호에 있어서 강력한 비화 방식이다. 본 논문에서는 KAISER WINDOW FIR 필터를 이용하여 호핑 필터를 구성하였으며, 이차원진폭 스크램블링 알고리즘의 최대 단점인 동기(synchronization)문제를 해결하기 위하여 variable delay를 이용한 알고리즘을 제안하였다. 또한, 시뮬레이션을 통하여 디지탈 신호에도 응용·고찰하였다.

• Proceedings of the IEEK Conference
• /
• 2001.09a
• /
• pp.951-954
• /
• 2001

본 논문에서는 SDR (Software Defined Radio)시스템을 위한 디지털 IF (Intermediate Frequency)수신기를 구현하였다[1][2]. 구현된 수신기의 하드웨어 구조는 AD변환부, PDC(Programmable Down Converter)부, DSP (Digital Signal Processing)부분으로 이루어졌다. AD변환부는 Analog Devices사의 AD6644를 이용하여 아날로그 신호를14bit의 디지털 신호로 변환된다. PDC부분은 Intersil사의 HSP 50214B를 이용하여 14bit 샘플 된 IF(Intermediate Frequency)입력을 혼합기와 NCO(Numerically Controlled Oscillator)에 의해 기저대역으로 다운 시키는 역할을 한다. PDC는 CIC (Cascaded Integrator Comb)필터, Halfband 필터 그리고 프로그램할 수 있는 FIR필터로 구성되어 있다. 그리고 PDC부분을 제어하고 PDC부분에서 처리할 수 없는 캐리어, 심볼 트래킹을 위해 Texas Instrument사의 16비트의 고정소수점 DSP인 TMS320C5416과 Altera사의 FPGA를 사용하였다. 그러므로 중간주파수 대역과 기저대역 간의 신호변환을 디지털 신호처리를 수행함으로써 일반적인 아날로그 처리방식보다 고도의 유연성과 고성능 동작이 가능하고 시간과 환경 변화에 우수한 동작 특성을 제공한다.

• Journal of the Institute of Electronics Engineers of Korea SC
• /
• v.40 no.3
• /
• pp.93-98
• /
• 2003

With the improvement of digital signal processors, digital pulse compressor(DPC) is widely used in radar systems. The DPC can be implemented by using FIR filter algorithm in time domain or FFT algorithm in frequency domain. This paper designs an expansible DPC using multiple DSPs. With ADSP-21060 of Analog Devices Inc., the computation time as a function of the number of received range cells and FIR filter tap is compared and analyzed in time domain using C-language and assembly language. therefore, when radar system parameters are determined, the number of DSP's required to implement DPC can be easily estimated.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.31 no.1C
• /
• pp.65-73
• /
• 2006

The purpose of this study is to design and analyze the pre-modulation filter with the variable -3dB cutoff frequency and linear phase response for bandlimiting the allocation of radio frequency bandwidth in PCM/FM transmission system. For the implementation of this required filter, the digital FIR filter, DAC and variable 2nd order LPF have been constructed with the filter block which designed and analyzed by each stage in order to satisfy the attenuation characteristic requirement of the analog 7th order bessel filter. The paper also concerned the linear phase properties for the filter block. Especially we have carried out the linear phase simulation with real parts for variable 2nd order LPF and compared this simulation results with the one of the fixed bandwidth 2nd order bessel filter for validating the linear phase requirement.

• Journal of IKEEE
• /
• v.3 no.1 s.4
• /
• pp.11-21
• /
• 1999

This paper has been proposed a structure composed of FIRs and IIR filters as digital interpolation filter to integrate the off-chip analog low-pass filter of audio DAC. The passband ripple (>$0.41{\times}fs$), passband attenuation(>at$0.41{\times}fs$) and stopband attenuation(<$0.59{\times}fs$) of the ${\Delta}{\Sigma}$ modulator output using the proposed digital interpolation filter had ${\pm}0.001[dB]$, -0.0025[dB] and -75[dB], respectively. Also the inband group delay was 30.07/fs[s] and the error of group delay was 0.1672%. Also, the attenuation of stopband has been increased -20[dB] approximately at 65[kHz], out-of-band. Therefore the RC products of analog low-pass filter on chip have been decreased compared with the conventional digital interpolation filter structure.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.31 no.7C
• /
• pp.713-724
• /
• 2006

The purpose of this study is to design, implement and verify the pre-modulation filter with the variable -3dB cutoff frequency and linear phase response for bandlimiting the allocation of radio frequency bandwidth for PCM/FM transmission. For the design of this required filter, the digital FIR filter, DAC system and tuneable 2nd order LPF have been constructed and simulated according to the attenuation characteristic requirement of the amplitude frequency response by each stage. From these results, we have implemented the filter and verified the analog conversion hardware part which is composed of DAC system and tuneable 2nd order LPF for the interpolation of the discrete sequences. Especially this paper proposes and carries out the verification processes using the tone generator and the calibration procedures for more precise frequency response of the filter.