• Journal of the Korea Computer Industry Society
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• v.3 no.1
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• pp.27-34
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• 2002

There is much interest on information communications owing to the rapid development of network and IT(Information Technology). Analog signals are converted into digital signals for information communications. However, it is very difficult to completely erase the distortion induced during the conversion of analog signals such as voices and images into digital signals. Existing audio graphic equalizer requires very complex processes to calculate the gain and coefficients of the higher-order filter which is required to generate natural sound and to satisfy the need of each person. Unfortunately it is uneconomical and very difficult to embed the existing digital audio equalizer in the system because of the complexity of the existing digital audio equalizer for high quality sound. This paper discusses the design of a new digital audio graphic equalizer(DAGEQ) which can improve system performance and the quality of audio sound, and can be embedded in the system. This new DAGEQ is designed so that the gain can be controlled automatically. The automatic control of coefficients and gain empowers real time processing and the improvement of audio quality.

• Proceedings of the Korea Water Resources Association Conference
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• 2010.05a
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• pp.1461-1465
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• 2010

산업기술의 발전은 자연현상에서 발생되는 다양한 형태의 아날로그 신호를 디지털 신호로 변환할 수 있게 되었으나, 자연현상의 신호는 그 정보량이 상당할 뿐만 아니라 디지털 신호로 변환하는 과정에서 발생되는 계통오차 및 동역학적 노이즈 등이 포함되어 있어 신호 해석에 많은 어려움이 있다. 최근 유량조사 분야에서도 최첨단 유량측정 기술인 초음파 유량계 설치를 통하여 기존의 유량조사 방법으로 불가능했던 감조하천과 대하천에서의 실시간 유량자료를 생산하고 있으며, 이에 근거하여 홍수예보 및 하천관리 업무에 효과적으로 활용하고 있다. 본 연구에서는 초음파 유량계가 설치된 여주지점의 2009년도 자동유량측정성과 중 동역학적 노이즈이라 판단되는 신호에 대하여 노이즈저감에 관한 방법론을 검토하고자 한다. 이를 위해 노이즈저감과 시간과 주파수 영역에서 유연한 분해능을 갖는 웨이블릿 변환을 적용하였으며 다양한 웨이블릿 변환함수 중 'db4'를 이용하였다. 여주지점의 자동유량측정성과에 대한 웨이블릿 변환함수 'db4'를 적용한 결과, 30분 이하의 단주기 성분(D1 등)은 동역학적 노이즈으로 판단되었으며, 최종파형분해단계의 근사성분은 원자료에 근사한 결과값을 얻을 수 있었다. 또한, 최종 분해된 자료는 충주조정지댐 방류량과의 상 하류 유출량 분석과 유출률 분석에서 물리적으로 해석이 가능한 결과 값을 얻을 수 있었다.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.11
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• pp.36-42
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• 2007

In this paper, we have studied temperature compensation architecture for a bust mode optical transmitter to convert the electric burst mode date signal to a optical one through the laser diode. In order to get stable high speed data transmission, we used digital sampling technique with a microprocessor for the temperature compensation of the laser diode, not the previous real time analog technique. Though the digital automatic power control circuit should be complemented the previous analog one with accuracy and effectiveness. So the digital technique will be more effective in further future in development for the over Gb/s transmitting speed.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.14 no.4
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• pp.1903-1907
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• 2013

Heart condition should be observed for long periods of time because it does not appear abnormal all the time. However, there are many difficulties checking our health for a long time due to its size, operation of equipment, and cost. To solve these problems, an electrocardiograms(ECG), specially interfacing three gel-less metal electrodes for low cost portable applications, is designed and implemented. Gel-less metal electrodes are used for ECG monitoring system instead of gel-type electrodes that can cause skin rashes and itching problem. The whole ECG system consists of two parts-analog and digital circuits. The analog measurement circuit that has a 18*25mm size is made up of op-amps maintaining a sufficiently high common-mode noise rejection and passive elements of SMD type. Analog heart signal is converted to digital stream suitable for display on a TFT-LCD by an 8-bit microcontroller. The size of the completed ECG system is 25*80*50mm and its weighing is about 150g, which is small enough to be easily used. Therefore, the implemented ECG system can be used as a portable one.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.23 no.12
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• pp.1673-1678
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• 2019

There are various networks and communication methods are used in industrial communication. Enterprises need to convert communications between industrial devices and networks for production line expansion, factory upgrades, network segmentation, and SI. This requires designers manufactured by many manufacturers to provide communication equipment for data or protocol conversion in order to connect and transmit various other mechanical devices to the network. This paper designed industrial communication gateway that can support the transformation of industrial communication protocol using multi-layered communication module. Industrial communication gateways have a structure that connects individual communication modules using RS485 communication to multiple layers. Each communication module consisted of analog and digital data card, LAN, and CAN-enabled card. The main board processor used Atmega micro-processor, and the RS485 slot was placed to have a multi-layer communication module structure. These additive layer type communication modules support analog and digital I/O functions and LAN and CAN for wide use in industrial communication control and monitoring.

• Journal of the Institute of Convergence Signal Processing
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• v.8 no.3
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• pp.205-210
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• 2007

This paper presents a CMOS TIQ flash A/D converter which operates very fast compared to other types of A/D converters due to its parallel architecture. The output resolution of designed A/D converter is 6-bit. In order to reduce the power consumption and chip area of conventional flash A/D converter, TIQ based flash A/D converter is proposed, which uses the advantage of the structure of CMOS transistors. The length and width of transistors of TIQ were determined with HSPICE simulation. To speed up the ultra-high speed flash A/D converter, the Fat Tree Encoder technique is used. The TIQ A/D converter was designed with full custom method. The chip's maximum power consumption was 38.45mW at 1.8V, and the operating speed of simulation was 2.7 GSPS.

• Journal of the Korean Institute of Intelligent Systems
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• v.13 no.4
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• pp.397-402
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• 2003

This paper concerns a pulse-width-modulation (PWM) controller design technique using digital redesign. Digital redesign is to convert a well-designed analog controller into an equivalent pulse-amplitude-modulation (PAM) controller maintaining the original analog control system in the sense of state-matching. In similar line of conversion concept, the redesigned PAM controller is converted into a PWM controller using the equivalent area principle. To convincingly visualize the proposed technique, an computer simulation example-attitude control of artificial satellite system is included.

• Journal of the Korean Society for Aeronautical & Space Sciences
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• v.49 no.11
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• pp.933-940
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• 2021

The space-borne SAR(Synthetic Aperture Radar) system radiates the microwave signal and receives the backscattered signal. The received signal is converted to digital at the Digital Receiver, which is implemented at the end of the SAR sensor receiving chain. The converted signal is formated after signal processing such as filtering and data compression. Two quantization are conducted in the Digital Receiver. One quantization is an analog to digital conversion at ADC(Analog-Digital Converter). Another quantization is the BAQ(Block Adaptive Quantization) for data compression. The quantization process is a conversion from a continuous or higher bit precision to a discrete or lower bit precision. As a result, a quantization noise is inevitably occurred. In this paper, the impact of two quantization processes are analyzed in a view of SNR degradation.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.24 no.8A
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• pp.1252-1258
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• 1999

This paper describes a COMS IF transceiver IC for 10-MHz bandwidth wireless local loops. It interfaces between the RF section and the digital MODEM section and performs the IF-to-baseband (Rx) and baseband-to-IF (Tx) frequency conversions. The chip incorporates variable gain amplifiers, phase-locked loops, low pass filters, analog-to-digital and digital-to-analog converters. It has been implemented in a 0.6 -${\mu}{\textrm}{m}$ 2-poly 3-metal CMOS process. The phase-locked loops include voltage-controlled oscillators, dividers, phase detectors, and charge pumps on chip. The only external complonents are the filter and the varactor-tuned LC tank circuit. The chip size is 4 mm $\times$ 4 mm and the total supply current is about 57 mA at 3.3 V.

• Journal of IKEEE
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• v.25 no.2
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• pp.302-308
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• 2021

A 12-bit 10-MS/s pipeline analog-to-digital converter (ADC) is proposed for image processing applications. The proposed pipeline ADC consists of a sample and hold amplifier, three stages, a 3-bit flash analog-to-digital converter, and a digital error corrector. Each stage is operated by using a 4-bit flash ADC (FADC) and a multiplying digital-to-analog converter (MDAC). The proposed sample and hold amplifier increases the voltage gain using gain boosting for the ADC with high resolution. The proposed pipelined ADC is designed using a 180-nm CMOS process with a supply voltage of 1.8 and it has an effective number of bit (ENOB) of 10.52 bits at sampling rate of 10MS/s for a 1-V_pp differential sinusoidal analog input with frequency of 1 MHz. The measured ENOB is 10.12 bits when the frequency of the sinusoidal analog input signal is a Nyquist frequency of approximately 5 MHz.