• Journal of the Korea Institute of Information and Communication Engineering
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• v.16 no.5
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• pp.999-1008
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• 2012

Unlike the existing CMOS chip, ISB (Intelligent Silicon Bead) is new concept biochip equipped with optical communication and memory function. It uses the light for power of SoC CMOS and interface with external devices therefore it is possible to miniaturize a chip size and lower the cost. This paper introduces an input protocol and a design of the low power and the low area to transfer the power and the signal through a single optical signal applied from external reader device to bead chip at the same time. It is also verified through simulation and measurement. In addition, low-power PROM is designed for recording and storing ID of a chip and it is successful in obtaining the value of output according to the optical input. Through this study, a new type biochip development can be expected by solving high cost and a limit of miniaturizing a chip area problem of an existing RFID.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.25 no.1
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• pp.130-136
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• 2014

This paper reviews the research on silicon based phased array system operating from microwave to millimeter wave frequencies. First, the design of phase shifter using CMOS technology is presented. The passive phase shifter is applied to the transmit/receive module from one to 16 channel in a single chip. The 35 GHz 4-element T/R module consumes less than 200 mW both transmit and receive modes. The architecture can extend to 16-channel operating at 44 GHz, thereby improving transmit power and linearity. The Ku-band 2-antenna 4-element receiver was developed using active phase shifter based on vector sum method. It is important to minimize coupling between beams because the chip contains four independent beams. The method of coupling is presented and verified.

• Journal of the Microelectronics and Packaging Society
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• v.15 no.1
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• pp.65-69
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• 2008

This work shows that the grinding-induced scratches formed on the back surface of silicon chips can highly influence the flexural strength of the chips. Meanwhile, in a case that excellent adhesion between the back surface and the plastic package body maintains, the flexural strength of plastic-encapsulated packages is not so sensitive to the geometry of the scratch marks. This article explains why such different flexural fracture behavior between bare chips and plastic-encapsulated chips appears.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.39 no.11
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• pp.40-46
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• 2002

A MEMS(Micro Electro Mechanical System) package using a doped-silicon(Si) carrier for coplanar microwave and millimeter-wave integrated circuits is proposed in order to reduce parasitic problems of leakage, coupling and resonance. The proposed carrier scheme is verified by fabrication and measuring a GaAs CPW(Coplanar Waveguide) on the three types of Si-carriers(gold-plated high resistivity, lightly doped, high resistivity). The proposed MEMS package using the lightly doped(15 ${\Omega}{\cdot}$) Si-carrier shows parasitic-free performance since the lossy Si-carrier effectively absorbs and suppresses the resonant leakage.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.6 no.1
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• pp.99-102
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• 2002

Pinholes on the thermally grown oxide, which is called gate oxide, on silicon substrate under polysilicon layer are found and its mechanism is analyzed in this paper. The oxide under a polysilicon layer is broken during the plasma etching process of other polysilicon layer. Both polysilicon layers are separated with 0.8${\mu}{\textrm}{m}$ thick oxide deposited by CVD (Chemical Vapor Deposition). Since broken oxide points are found scattered around an arc occurrence point, it is assumed that an extremely high electric field generated near the arc occurrence point makes the gate oxide broken. 1'he arc occurrence point has been observed on the alignment key and is the mark of low yield. It is found that any arc occurrence can cause chips to fail by breaking the gate oxide, even if are occurrence points are found on scribeline.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.5 s.347
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• pp.48-53
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• 2006

This paper describes the electrical characteristics of monolithic optical transceiver circuitry being used in the fiber optic modules. It has been designed and fabricated, and compared with two chips version transceiver when operates at 155.52 Mbps data rates. To avoid noise and interference between transmitter and receiver on one chip, layout techniques such as special placement, power supply separation, guard ring, and protection wall were used in the design. To compare the two kind of fiber optic modules using each chip, single chip version has similar properties to two chip version in the electrical characteristics as noise and others.

• 한국신재생에너지학회:학술대회논문집
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• 2011.05a
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• pp.111.2-111.2
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• 2011

야금학적 방법을 통한 태양전지용 실리콘 제조를 위하여 아크로(Arc furnace)에서 제조된 용융 상태의 금속급 실리콘을 슬래그와 직접 반응시켜 불순물을 제거하는 공정에 관한 연구를 수행하였다. 이를 위해 아크로와 고주파 유도용해로(High-frequency induction furnace)를 이용하여 금속급 실리콘을 제조와 정련 특성 실험을 수행하였다. 본 연구에서 금속급 실리콘을 제조하기 위한 장비로 150kW급-DC 아크로와 300kW급-AC 아크로를 사용하였다. 원재료로 규석, 코크스(Cokes), 숯, 그리고 우드칩(Wood chip)을 실험 비율에 맞춰 아크로 내부에 장입하고, 이를 용융환원 방법을 통해 반응을 시켰다. 이때 생산된 금속급 실리콘의 순도는 약 99.2~99.8% 이었으며, 원재료의 순도, 장입 비율 및 아크로 운전 특성에 따라 편차가 있다. 아크로에서 생산된 금속급 실리콘의 경우 인(phosphorus), 붕소(boron)를 다량 함유하고 있고, 이를 제거하기 위하여 50kW급 고주파 유도용해로 장비를 사용하여 슬래그 정련 실험을 수행하였다. 슬래그 정련시 사용한 성분은 SiO2, CaO 그리고 CaF2 이며, 금속급 실리콘과 슬래그의 질량비 및 반응 시간에 따른 실리콘 불순물 특성을 평가하였다. 실험결과 인과 붕소는 각각 1 ppm 이하, 5 ppm 이하 였으며, 칼슘을 제외한 대부분의 금속 불순물의 경우 0.1~0.2% 임을 확인하였다.

• 한국신재생에너지학회:학술대회논문집
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• 2011.11a
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• pp.54.2-54.2
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• 2011

야금학적 정련 공정 중 슬래그 처리, 일방향 응고, 플라즈마-전자기유도용해 공정을 적용한 태양전지용 실리콘 제조 기술에 관한 연구를 수행하였다. 원소재인 금속급 실리콘을 제조하기 위해원재료로 규석, 코크스(Cokes), 숯, 그리고 우드칩(Wood chip)을 사용하였으며, 150kW급 DC 아크로(Arc furnace)를 이용하여 순도 99.8% 금속급 실리콘을 제조하였다. 제조된 용융 상태의 금속급 실리콘은 슬래그와 반응시켜 불순물을 제거하였다. SiO2-CaO-CaF2 계의 슬래그를 이용하였으며, 금속급 실리콘과 슬래그의 질량비 및 반응 시간에 따른 실리콘 불순물 특성을 평가하였다. 이후 고액 계면이 제어 가능한 일방향 응고 장치를 이용하여 금속불순물을 제거하였다. 고액상태의 온도 조건 및 응고 시간에 따른 불순물 농도 변화를 평가하였으며, 순도 6N급의 실리콘을 제조하였다. 마지막 공정으로 스팀 플라즈마 토치와 냉도가니가 적용된 전자기 유도 용해장치를 이용하여 붕소와 인을 제거하였다. 플라즈마 토치 가스로는 아르곤, 스팀, 수소를 이용하였다. 붕소와 인의 제거율은 각각 94%와 96%를 달성하였으며, 최종 순도 6N급의 실리콘을 제조하였다.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.9
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• pp.11-17
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• 2004

This paper describes the implementation of monolithic optical transceiver circuitry being used as a part of the fiber optic modules. It has been fabricated in 0.6 ${\mu}{\textrm}{m}$ 2-poly 3-metal silicon CMOS analog technology and operates at 155.52 Mbps(STM-1) data rates. It drives laser diode to transmit intensity modulated optical signal according to 155.52 Mbps electrical data from system. Also, it receives 155.52 Mbps optical data that transmitted from other systems and converts it to electrical data using photo diode and amplifier. To avoid noise and interference between transmitter and receiver on one chip, layout techniques such as special placement, power supply separation, guard ring, and protection wall were used in the design. The die area is 4 ${\times}$ 4 $\textrm{mm}^2$, and it has 32.3 ps rms and 335.9 ps peak to peak jitter on loopback testing. the measured power dissipation of whole chip is 1.15 W(230 mW) with a single 5 V supply.

• Journal of IKEEE
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• v.7 no.2 s.13
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• pp.245-252
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• 2003

We designed a silicon pressure sensor interface circuit with digital calibration capability. The interface circuit is composed of an analog section and a digital section. The analog section amplifies the weak signal from the sensor and the digital section handles the calibration function and communication function between the chip and outside microcontroller that controls the calibration. The digital section is composed of I2C serial interface, memory, trimming register and controller. The I2C serial interface is optimized to suit the need of on-chip silicon microsensor in terms of number of IO pins and silicon area. The major part of the design is to build a controller circuit that implements the optimized I2C protocol. The designed chip was fabricated through IDEC's MPW. We also made a test board and the test result showed that the chip performs the digital calibration function very well as expected.