• E2M - 전기 전자와 첨단 소재
• /
• 제8권2호
• /
• pp.165-170
• /
• 1995

This paper describes the fabrication and characteristics of a Si Hall sensor fabricated on a SOI (Si-on-insulator) structure. The SOI structure was formed by SDB(Si-wafer direct bonding) technology and the insulator of the SOI structure was used as the dielectrical isolation layer of a Hall sensor. The Hall voltage and sensitivity of the implemented SDB SOI Hall sensors showed good linearity with respect to the applied magnetic flux density and supplied current. The product sensitivity of the SDB SOI Hall sensor was average 600V/A.T and its value has been increased up to 3 times compared to that of bulk Si with buried layer of 10.mu.m. Moreover, this sensor can be used at high-temperature, high-radiation and in corrosive environments.

• 한국산학기술학회:학술대회논문집
• /
• 한국산학기술학회 2001년도 추계산학기술 심포지엄 및 학술대회 발표논문집
• /
• pp.169-172
• /
• 2001

다층 MEMS구조의 기초기판쌍 소재로 쓰일 수 있는 Si∥SiO₂/Si₃N₄∥Si 기판쌍의 직접접합 가능성을 확인하기 위해서 2000Å-SiO₂와 500Å-Si₃N₄층을 가진 직경 10cm의 실리콘 기판을 각각 친수성 및 소수성 표면세척을 하고 청정분위기에서 경면끼리 가접을 실시하였다. 가접된 기판쌍을 통상의 박스형 전기로를 이용하여 400, 600, 800, 1000, 1200℃ 범위에서 2시간 동안 가열하여 접합을 완료하였다. 완성된 기판쌍을 적외선분석기를 이용하여 접합면적을 확인하였고, 면도칼 삽입법으로 접합계면에너지를 측정하였다. 실험온도 범위 내에서 Si∥SiO₂/Si₃N₄∥Si 기판쌍은 1000℃ 이상에서 접합계면에너지는 2,344mJ/㎡을 나타냈으며, 이는 기존의 Si/Si의 동종접합기판쌍과 동등한 수준의 접합강도로서 부가가치가 큰 새로운 조합의 기판쌍 제조가 가능하였다.

• 한국전기전자재료학회:학술대회논문집
• /
• 한국전기전자재료학회 1999년도 춘계학술대회 논문집
• /
• pp.370-373
• /
• 1999

Si direct bonding (SDB) technology is very attractive for both Si-on-insulator(SOI) electric devices and MEMS applications because of its stress free structure and stability. This paper presents on- pre treatment conditions in Si wafer direct bonding, The paper resents on pre-bonding according to HF pre-treatment conditions in Si wafer direct bonding. The characteristics of bonded sample were measured under different bonding conditions of HF concentration, applied pressure and annealing temperature(200~ 100$0^{\circ}C$) after pre-bonding. The bonding strength was evaluated by tensile strength method. The bonded interface and the void were analyzed by using SEM and IR camera, respectively, Components existed in the interlayer were analyzed by using FT-IR. The bond strength depends on the HF pre-treatment condition before pre-bonding(Min 2.4kgf/$\textrm{cm}^2$~ Max : 14.kgf/$\textrm{cm}^2$)

• 한국전기전자재료학회:학술대회논문집
• /
• 한국전기전자재료학회 2000년도 추계학술대회 논문집
• /
• pp.583-586
• /
• 2000

The non-selective method by polishing after grinding was used widely to thinning of SDB SOI structures. This method was very difficult to thickness control of thin film, and it was dependent on equipments. However electrochemical etch-stop, one of the selective methods, was able to accurately thickness control and etch equipment was very simple. Therefore, this paper described with the effect of leakage current and electrodes on electrochemical etch-stop. Consequentially, PP(passivation potential) was changed according to the kinds of contact and contact sizes, but OCP(open current potential) was not change with range of -1.5~-1.3V

• 한국전기전자재료학회:학술대회논문집
• /
• 한국전기전자재료학회 2000년도 추계학술대회 논문집
• /
• pp.579-582
• /
• 2000

This paper described on the fabrication of SOI(Si-on-insulator) structures with buried cavities by SDB technology and eletrochemical etch-stop. The cavity was fabricated the upper handling wafer by Si anisotropic etch technique. SDB process was performed to seal the fabricated cavity under vacuum condition at -760mmHg. In the SDB process, captured air and moisture inside of the cavities were removed by making channels towards outside. After annaling(100$0^{\circ}C$, 60 min.), the SDB SOI structure was thinned by electrochemical etch-stop. Finally, it was fabricated the SDB SOI structure with buried cavities as well as an accurate control and a good flatness.

• 한국전기전자재료학회논문지
• /
• 제13권5호
• /
• pp.431-436
• /
• 2000

This paper describes on the fabrication of a SOI substrate by SDB technology and electrochemical etch-stop. The surface of the thinned SDB SOI substrate is more uniform than that of grinding or polishing by mechanical method and this process was found to be a very accurate method for SOI thickness control. During electrochemical etch-stop leakage current versus voltage curves were measured for analysis of the open current potential(OCP) point the passivation potential(PP) point and anodic passivation potential. The surface roughness and the controlled thickness selectivity of the fabricated a SDB SOI substrate were evaluated by using AFM and SEM respectively.

• 한국전기전자재료학회:학술대회논문집
• /
• 한국전기전자재료학회 2000년도 춘계학술대회 논문집 전자세라믹스 센서 및 박막재료 반도체재료 일렉트렛트 및 응용기술
• /
• pp.126-129
• /
• 2000

This paper describes on the fabrication of a SOI substrate by SDB technology and electrochemical etch-stop. The surface of the thinned SDB SOI substrate is more uniform than that of grinding or polishing by mechanical method, and this process was found to be very accurate method for SOI thickness control. During electrochemical etch-stop, leakage current versus voltage curves were measured for analysis of the open current potential (OCP) point, the passivation potential (PP) point and anodic passivation potential. The surface roughness and the controlled thickness selectivity of the fabricated a SDB SOI substrate were evaluated by using AFM and SEM, respectively.

• 한국전기전자재료학회:학술대회논문집
• /
• 한국전기전자재료학회 2000년도 영호남학술대회 논문집
• /
• pp.301-306
• /
• 2000

This paper describes on the fabrication of a SOI substrate by SDB technology and electrochemical etch-stop. The surface of the thinned SDB SOI substrate is more uniform than that of grinding or polishing by mechanical method, and this process was found to be a very accurate method for SOI thickness control. During electrochemical etch-stop, leakage current versus voltage curves were measured for analysis of the open current potential(OCP) point, the passivation potential(PP) point and anodic passivation potential. The surface roughness and the controlled thickness selectivity of the fabricated a SDB SOI substrate were evaluated by using AFM and SEM, respectively.

• 한국전기전자재료학회:학술대회논문집
• /
• 한국전기전자재료학회 1994년도 추계학술대회 논문집
• /
• pp.86-89
• /
• 1994

This paper describes the fabrication and basic characteristics of a Si Hall device fabricated on a SOI(Si-on-insulator) structure. In which SOI structure was formed by SOB(Si-wafer direct bonding) technology and the insulator of the SOI structure was used as the dielectrical isolation layer of a Hall device. The Hall voltage and sensitivity of the implemented SDB SOI Hall devices showed good linearity with respectivity to the applied magnetic flux density and supple iud current. The product sensitivity of the SDB SOI Hall device was average 670 V/A$.$T and its value has been increased up to 3 times compared to that of bulk Si with buried layer of 10$\mu\textrm{m}$. Moreover, this device can be used at high-temperature, high-radiation and in corrosive environments.

• 한국재료학회지
• /
• 제11권5호
• /
• pp.427-430
• /
• 2001

절연 특성이 기존의 SiO$_2$ 보다 우수한 500 두께의 SiN$_4$층을 두 단결정 실리콘사이의 절연막질로 채택하고 직접접합시켜 직경 10cm의 Si(100) /500 -Si$_3$N$_4$/Si (100) 기판쌍을 제조하였다. p-type (100) 실리콘기판을 친수성, 소수성을 갖도록 습식방법으로 세척한 두 그룹의 시편들을 준비하였다. 기판전면에 LPCVD로 500 $\AA$ 두께의 Si$_3$N$_4$∥Si(100) 기판을 성장시키고 실리론 기판과 고청정상태에서 가접시킨 후, 선형열원의 이동속도를 0.1mm/s로 고정시키고 선형 입열량을 400~1125w 범위에서 변화시키면서 직접접합을 실시하였다. 접합된 기판은 적외선 카메라로 계면 접합면적을 확인하고 razor blade creek opening 측정법으로 세정 방법에 따른 각 기판쌍 그들의 접합강도를 확인하였다. 접합강도가 측정된 기판쌍은 high resolution transmission electron microscopy (HRTEM )을 사용하여 수직단면 미세구조를 조사하였다. 입열량의 증가에 따라 두 그를 모두 접합율은 큰 유의차 없이 765% 정도로, 소수성 처리가 된 기판쌍의 접합강도는 1577mJ/$m^2$가지 선형적으로 증가하였으나, 친수성 처리가 된 기판쌍은 주어진 실험 범위에서 입열량의 증가에 따라 큰 변화 없이 2000mj/$m^2$이상의 접합 강도를 보였다 친수성 처리가 된 기판쌍의 수직단면 미세구조를 고분해능 투과전자현미경으로 각인한 결과 모든 시편의 실리콘과 Si$_3$N$_4$사이에 25 $\AA$ 정도의 SiO$_2$ 자연산화막이 존재하여 중간충 역할을 함으로서 기판접합강도를 향상시키는 것으로 판단되었다.