• Journal of the Institute of Convergence Signal Processing
• /
• v.2 no.3
• /
• pp.93-101
• /
• 2001

In this paper, we propose an image downscaler used in multimedia video applications, such as DTV, TV-PIP, PC-video, camcorder, videophone and so on. The proposed image downscaler provides a scaled image of high-quality and high-performance. This paper will explain the scaling theory using two-dimensional digital filters. It is the method that removes an aliasing noise and decreases the hardware complexity, compared with Pixel-drop and Upsamling. Also, this paper will prove it improves scaling precisians and decreases the loss of data, compared with the Scaler32, the Bt829 of Brooktree, and the SAA7114H of Philips. The proposed downscaler consists of the following four blocks: line memory, vertical scaler, horizontal scaler, and FIFO memory. In order to reduce the hardware complexity, the using digital filters are implemented by the multiplexer-adder type scheme and their all the coefficients can be simply implemented by using shifters and adders. It also decreases the loss of high frequency data because it provides the wider BW of 6MHz as adding the compensation filter. The proposed downscaler is modeled by using the Verilog-HDL and the model is verified by using the Cadence simulator. After the verification is done, the model is synthesized into gates by using the Synopsys. The synthesized downscaler is Placed and routed by the Mentor with the IDEC-C632 0.65${\mu}{\textrm}{m}$ library for further IC implementation. The IC master is fixed in size by 4,500${\mu}{\textrm}{m}$$\times$4,500${\mu}{\textrm}{m}$. The active layout size of the proposed downscaler is 2,528${\mu}{\textrm}{m}$$\times$3,237${\mu}{\textrm}{m}$.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.43 no.12 s.354
• /
• pp.47-54
• /
• 2006

This work proposes a dual-channel 6b 1GS/s ADC for ultra wide-band communication system applications. The proposed ADC based on a 6b interpolated flash architecture employs wide-band open-loop track-and-hold amplifiers, comparators with a wide-range differential difference pre-amplifier, latches with reduced kickback noise, on-chip CMOS references, and digital bubble-code correction circuits to optimize power, chip area, and accuracy at 1GS/s. The ADC implemented in a 0.18um 1P6M CMOS technology shows a signal-to-noise-and-distortion ratio of 30dB and a spurious-free dynamic range of 39dB at 1GS/s. The measured differential and integral non-linearities of the prototype ADC are within 1.0LSB and 1.3LSB, respectively. The dual-channel ADC has an active area of $4.0mm^2$ and consumes 594mW at 1GS/s and 1.8V.

• Journal of the Institute of Convergence Signal Processing
• /
• v.8 no.1
• /
• pp.58-62
• /
• 2007

Digital communication is important for reliability and mobilization of the multi-channel communication systems. Transmitting and receiving data for the mobilization should be possible in anywhere and in anytime. And this system must be designed light weight small size and low power. One are essential technology for implementing the mobile wireless communication system on the age of ubiquotos. Requirements in constructing such communication field are followings. At first data transmitting and receiving should be carried out by a simple command. Second, the device should be designed as hand-hold type and low power consumption. Third, data communication should be reliable. As one of examples, car to car system which is popular in the market is introduced here, All traffic information in highway is transmitted from one car to another by using this system which can prevent possible traffic accident. This paper shows the design of a digital data communication system with CC1020 chip. This CC1020 makes easy frequency selection and easy switch from the transmit mode to the receive mode by simple setting of a memory register in the chip. The transmit power of this system is designed 10dBm and its communication range is about 100m. The power supplied this system is 3V considered as low power. The sleep mode can be easily entered during transmit mode or receive mode. We shows the program algorithm of CC1020 and interface circuit between MCU and CC1020. We shows the Photo of the CC1020 Module and Atmega128 Module.. We analysed the receiver rate with this system.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.29 no.1C
• /
• pp.102-110
• /
• 2004

In this paper, we propose a VLSI structure of real-time image compression and reconstruction processor using 2-D discrete wavelet transform and implement into a hardware which use minimal hardware resource using ASIC library. In the implemented hardware, Data path part consists of the DWT kernel for the wavelet transform and inverse transform, quantizer/dequantizer, the huffman encoder/huffman decoder, the adder/buffer for the inverse wavelet transform, and the interface modules for input/output. Control part consists of the programming register, the controller which decodes the instructions and generates the control signals, and the status register for indicating the internal state into the external of circuit. According to the programming condition, the designed circuit has the various selective output formats which are wavelet coefficient, quantization coefficient or index, and Huffman code in image compression mode, and Huffman decoding result, reconstructed quantization coefficient, and reconstructed wavelet coefficient in image reconstructed mode. The programming register has 16 stages and one instruction can be used for a horizontal(or vertical) filtering in a level. Since each register automatically operated in the right order, 4-level discrete wavelet transform can be executed by a programming. We synthesized the designed circuit with synthesis library of Hynix 0.35um CMOS fabrication using the synthesis tool, Synopsys and extracted the gate-level netlist. From the netlist, timing information was extracted using Vela tool. We executed the timing simulation with the extracted netlist and timing information using NC-Verilog tool. Also PNR and layout process was executed using Apollo tool. The Implemented hardware has about 50,000 gate sizes and stably operates in 80MHz clock frequency.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
• /
• 2021.05a
• /
• pp.611-613
• /
• 2021

Recently, research and development of quantum computers, which exceed the limits of classical computers, have been actively carried out in various fields. Quantum computers, which use quantum mechanics principles in a way different from the electrical signal processing of classical computers, have various quantum mechanical phenomena such as quantum superposition and quantum entanglement. It goes through a very complicated calculation process compared to the calculation of a classical computer for performing an operation using its characteristics. In order to utilize each element efficiently and accurately, it is necessary to visualize the data before driving the actual quantum computer and perform error verification, optimization, reliability, and verification. However, when visualizing all the data of various elements configured inside the quantum computer, it is difficult to intuitively grasp the necessary data, so it is necessary to visualize the data selectively. In this paper, we visualize the data of various elements that make up a quantum computer, and hierarchically visualize the internal circuit components of a quantum computer that are complicatedly configured so that the data can be observed and utilized intuitively.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
• /
• v.16 no.6
• /
• pp.454-464
• /
• 2023

This paper proposes a low-power 8-bit asynchronous SAR ADC with a sampling rate of 1 MS/s for sensor node applications. The ADC uses bootstrapped switches to improve linearity and applies a VCM-based CDAC switching technique to reduce the power consumption and area of the DAC. Conventional synchronous SAR ADCs that operate in synchronization with an external clock suffer from high power consumption due to the use of a clock faster than the sampling rate, which can be overcome by using an asynchronous SAR ADC structure that handles internal comparisons in an asynchronous manner. In addition, the SAR logic is designed using dynamic logic circuits to reduce the large digital power consumption that occurs in low resolution ADC designs. The proposed ADC was simulated in a 180-nm CMOS process, and at a 1.8 V supply voltage and a sampling rate of 1 MS/s, it consumed 46.06 𝜇W of power, achieved an SNDR of 49.76 dB and an ENOB of 7.9738 bits, and obtained a FoM of 183.2 fJ/conv-step. The simulated DNL and INL are +0.186/-0.157 LSB and +0.111/-0.169 LSB.

• Journal of Life Science
• /
• v.34 no.3
• /
• pp.170-178
• /
• 2024

Adipose-derived stem cells (ADSCs) are capable of differentiation into multiple lineages of cells, which has attracted attention for clinical therapy. However, ADSCs have poor proliferation capacity and a short life span in culture, which is an impediment in the application to clinical use. Previously, to overcome growth disadvantages, we had established an immortalized ADSC line (ADSC-T) by introducing the SV40 T antigen coding gene into primary human ADSC. In the present study, we evaluated the differentiation potential of this cell line and assessed the anti-inflammatory effect of its conditioned medium (CM). ADSC-T appeared to maintain the differentiation potential into adipocyte and chondrocyte. The CM of ADSC-T suppressed the NF-κB activity and its target gene expression of COX-2 and iNOS. Furthermore, the phosphorylations of MAPKs, including ERK, JNK and p38, were suppressed by the ADSC-T CM. The expressions of pro-inflammatory cytokines such as TGF-β, TNF-α, IL-6, and IL-13 were also suppressed by the CM of ADSC-T. In the Nc/Nga atopic model mice, the CM showed therapeutic effect on DNCB-induced atopic dermatitis. These results indicate that the immortalized ADSC-T maintains the beneficial properties of primary ADSC and could be a versatile cell source for not only research into ADSC but also for production of CM suitable for clinical application.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
• /
• 2008.05a
• /
• pp.411-414
• /
• 2008

The study is about simulation of optical circuit for oneself performance evaluation of Fiber Optic Gyro(FOG) closed-loop controller board. The Fiber Optic Interferometer Simulator is used a digital signal processing for cosine response specificity output of fiber optic coil about input rate. Response specificity of the fiber optic coil is $Vo(t)=K3[1+\cos\{K1(Vm(t)-Vm(t-{\tau}))+K2\}]$. Also the Fiber Optic Interferometer Simulator is able to confirm a output value with K1, K2 and K3 input. The fiber Optic Interferometer Simulator is able to oneself performance evaluation without fiber optical circuit. Because, it is the very same cosine response specificity of real fiber optic coil about input rate.

• Journal of Radiation Protection and Research
• /
• v.28 no.3
• /
• pp.173-182
• /
• 2003

A prototype liquid scillatillator system for measurement of multiple beta-labeled mixtures was developed and its characteristic was investigated. The signal processing system consists of two photomultiplier tubes and the coincident count circuit. The characteristic of the system was analyzed using 4 beta-labeled samples $(^3H,\;^{14}C,\;^{36}Cl\;and\;^{90}Sr)$. Beta spectra from the samples were obtained without radiation shielding, and the detection limits for each nuclides were estimated based on the spectra. The estimated detection limits were compared to the legal regulation values. It is found that the liquid radioactive nuclides are detectable well below the legal regulation values.

• Transactions of the Korean Society of Mechanical Engineers B
• /
• v.39 no.1
• /
• pp.29-36
• /
• 2015

Exact comparisons of the thermal conductivities of the base fluid and a nanofluid are very important in the early stages of nanofluid development. A simple procedure of measuring the thermal conductivity of the two fluids by the transient hot wire method and numerically dividing these values is used for this purpose. However, because the experiments are not performed simultaneously and the physical properties of the measurement system are sometimes not properly known, large errors are incurred during the evaluation process. This article proposes a new apparatus for thermal conductivity comparison where the working principle is mainly based on relative measurement rather than absolute measurement. The measuring circuit and data processing steps are explained in detail; a validation test was performed using the well-known glycerine and engine oil.