• Title/Summary/Keyword: 신호처리(signal processing)

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Development and Performance Test of High Speed Signal Processor for The Millimeter Wave Seeker (밀리미터파 탐색기 고속 신호처리장치 개발 및 시험기)

  • Ha, Chang-Hun;Park, Pan-Soo
    • Journal of the Institute of Electronics Engineers of Korea SP
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    • v.49 no.1
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    • pp.119-127
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    • 2012
  • This paper describes development and performance test of signal processor for the millimeter wave seeker. A ground to air guidance missile is required various beam patterns in order to counteract different kind of target. Therefore, we designed the hardware and software architecture considering flexibility. This signal processor consists of ADC, FPGA, DSP and etc. FPGA provides peripheral interface to DSP and convert digital IF signal to baseband signal. DSP performs signal processing, calculates target's information and controls devices. Each parts' hardware are connected in series and signal processing algorithms for various beam patterns are built in parallel.

A VLSI Architecture for the Real-Time 2-D Digital Signal Processing (실시간 2차원 디지털 신호처리를 위한 VLSI 구조)

  • 권희훈
    • Information and Communications Magazine
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    • v.9 no.9
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    • pp.72-85
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    • 1992
  • The throughput requirement for many digital signal processing is such that multiple processing units are essential for real-time implementation. Advances in VLSI technology make it feasible to design and implement computer systems consisting of a large number of function units. The research on a very high throughput VLSI architecture for digital signal processing applications requires the development of an algorithm, decomposition scheme which can minimize data communication requirements as well as minimize computational complexity. The objectives of the research are to investigate computationally efficient algorithms for solution of the class of problems which can be modeled as DLSI systems or adaptive system, and develop VLSI architectures and associated multiprocessor systems which can be used to implement these algorithms in real-time. A new VLSI architecture for real-time 2-D digital signal processing applications is proposed in this research. This VLSI architecture extends the concept of having a single processing units in a chip. Because this VLSI architecture has the advantage that the complexity and the number of computations per input does not increase as the size of the input data in increased, it can process very large 2-D date in near real-time.

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Multiband Enhancement for DEMON Processing Algorithms (대역 분할 처리를 통한 데몬 처리 성능 향상 기법)

  • Cheong, Myoung Jun;Hwang, Soo Bok;Lee, Seung Woo;Kim, Jin Seok
    • The Journal of the Acoustical Society of Korea
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    • v.32 no.2
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    • pp.138-146
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    • 2013
  • Passive sonars employ DEMON (Detection of Envelope Modulation on Noise) processing to extract propeller information from the radiated noise of underwater targets. Conventional DEMON processing improves SNR(Signal to Noise Ratio) characteristic by Welch method. The conventional Welch method overlaps several different time domain DEMON outputs to reduce the variance. However, the conventional methods have high computational complexity to get high SNR with correlated acoustic signals. In this paper, we propose new DEMON processing method that divides acoustic signal into several frequency bands before DEMON processing and averages each DEMON outputs. Therefore, the proposed method gathers independent acoustic signal faster than conventional method with low computational complexity. We prove the performance of the proposed method with mathematical analysis and computer simulations.

A Design of the Signal Processing Hardware Platform for OFDM Communication Systems (OFDM 통신 시스템을 위한 신호처리 하드웨어 플랫폼 개발)

  • Lee, Byung-Wook;Cho, Sung-Ho
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.33 no.6C
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    • pp.498-504
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    • 2008
  • In this paper, an efficient hardware platform for the digital signal processing for OFDM Communication systems is presented. The hardware platform consists of a single FPGA, two DSPs with 8000 MIPS of maximum at 1 GHz clock, 2-channel ADC and DAC supporting maximum 125 MHz sampling rate, and flexible data bus architecture, so that a wide variety of baseband signal processing algorithms for practical OFDM communication systems may be implemented and tested. The IEEE 802.16 software modem is also presented in order to verify the effectiveness and usefulness of the designed platform.

Ultrasonic Signal Processing Algorithm for Crack Information Extraction on the Keyway of Turbine Rotor Disk (터빈 로터 디스크 키웨이의 초음파 신호로부터 균열정보의 추출을 위한 신호처리 알고리즘의 개발)

  • Lee, Jong-Kyu;Seo, Won-Chan;Park, Chan;Lee, Jong-O;Son, Young-Ho
    • Journal of the Korean Society for Nondestructive Testing
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    • v.29 no.5
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    • pp.493-500
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    • 2009
  • An ultrasonic signal processing algorithm was developed for extracting the information of cracks generated around the keyway of a turbine rotor disk. B-scan images were obtained by using keyway specimens and an ultrasonic scan system with x-y position controller. The B-scan images were used as input images for 2-Dimensional signal processing, and the algorithm was constructed with four processing stages of pre-processing, crack candidate region detection, crack region classification and crack information extraction. It is confirmed by experiments that the developed algorithm is effective for the quantitative evaluation of cracks generated around the keyway of turbine rotor disk.

Variable Step LMS Algorithm using Fibonacci Sequence (피보나치 수열을 활용한 가변스텝 LMS 알고리즘)

  • Woo, Hong-Chae
    • Journal of the Institute of Convergence Signal Processing
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    • v.19 no.2
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    • pp.42-46
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    • 2018
  • Adaptive signal processing is quite important in various signal and communication environments. In adaptive signal processing methods since the least mean square(LMS) algorithm is simple and robust, it is used everywhere. As the step is varied in the variable step(VS) LMS algorithm, the fast convergence speed and the small excess mean square error can be obtained. Various variable step LMS algorithms are researched for better performances. But in some of variable step LMS algorithms the computational complexity is quite large for better performances. The fixed step LMS algorithm with a low computational complexity merit and the variable step LMS algorithm with a fast convergence merit are combined in the proposed sporadic step algorithm. As the step is sporadically updated, the performances of the variable step LMS algorithm can be maintained in the low update rate using Fibonacci sequence. The performances of the proposed variable step LMS algorithm are proved in the adaptive equalizer.

Detection of HF Narrowband Signal with Unknown Frequency Using DFT Power Spectrum Averaging (DFT 전력스펙트럼 평균화를 기반으로 한 미지의 주파수를 가진 단파대 협대역 신호의 검출)

  • 김명진;김성필;오종갑
    • Proceedings of the Korea Institute of Convergence Signal Processing
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    • 2000.08a
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    • pp.29-32
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    • 2000
  • 본 논문에서는 미지의 반송파주파수를 가진 협대역 신호의 존재를 광대역에서 검출하는 문제를 고려하였다. DFT 전력 스펙트럼을 평균화하여 주파수 영역에서 Neyman-Pearson criterion을 사용하여 신호를 검출하는 방법을 사용하였다. 평균화된 DFT 스펙트럼의 통계적 특성과 검출 threshold 및 검출 확률을 분석하여 보았다.

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Signal Detection Using Wavelet Transform in Fractional Brownian Motion (Fractional Brownian Motion 잡음환경 하에서 웨이브렛 변환을 이용한 신호의 검출)

  • 김명진
    • Proceedings of the Korea Institute of Convergence Signal Processing
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    • 2000.08a
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    • pp.21-24
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    • 2000
  • Fractional Brownian motion(fBm)은 long-term persistence 특성을 가진 자연 현상, 1/f 잡음, 깊이가 낮은 해저에서의 배경음향잡음 등을 모델링하는데 많이 사용된다. 이 fBm은 nonstationary 유색잡음이다. 이러한 유색잡음 환경 하에서 신호를 검출하기 위한 한 방법은 Fredholm 적분방정식의 해를 구하는 것이다. 이 방정식을 이산화 하면 잡음의 공분산 행렬의 역행렬이 포함되어 계산량이 많다 본 논문에서는 fBm 잡음의 공분산 행렬을 웨이브렛 변환하여 얻어지는 행렬, 즉 fBm의 멀티스케일 성분들의 공분산행렬은 밴드화된 블록들로 근사화할 수 있다는 성질을 이용하여 적은 계산량으로 신호를 검출하는 알고리즘을 제안한다.

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A Study on the Implementation and Performance Analysis of Software Based GPS L1 and Galileo E1/E5a Signal Processing (소프트웨어 기반의 GPS L1 및 갈릴레오 E1/E5a 신호 처리 구현 및 성능에 관한 연구)

  • Sin, Cheon-Sig;Lee, Sang-Uk;Yoon, Dong-Won;Kim, Jae-Hoon
    • Journal of Advanced Navigation Technology
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    • v.13 no.3
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    • pp.319-326
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    • 2009
  • In this paper, the key technologies of Navigation receiver for GNSS sensor station are presented as a development result of a GNSS ground station in ETRI. A wide-band antenna and RF/IF components and SW signal processing unit to cover the GPS and Galileo signals for GNSS receiver are developed and its performance is verified by using GPS live signal and GNSS RF signal simulator from SpirentTM. We also gather GIOVE-A signal by using H/W antenna and RF/IF units in IF-level as sampling frequency and bit number, 112MHz and 8bits, respectively by using the developed wide-band antenna and RF/IF components. Data acquisition is done by using commercial data acquisition device from National Instrument TM. The gathered data is fed into SW receiver to process Galileo E1 to verify Galileo signal processing by Galileo live signal from GIOVE-A.

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Radar Signal Processor Design Using FPGA (FPGA를 이용한 레이더 신호처리 설계)

  • Ha, Changhun;Kwon, Bojun;Lee, Mangyu
    • Journal of the Korea Institute of Military Science and Technology
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    • v.20 no.4
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    • pp.482-490
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    • 2017
  • The radar signal processing procedure is divided into the pre-processing such as frequency down converting, down sampling, pulse compression, and etc, and the post-processing such as doppler filtering, extracting target information, detecting, tracking, and etc. The former is generally designed using FPGA because the procedure is relatively simple even though there are large amounts of ADC data to organize very quickly. On the other hand, in general, the latter is parallel processed by multiple DSPs because of complexity, flexibility and real-time processing. This paper presents the radar signal processor design using FPGA which includes not only the pre-processing but also the post-processing such as doppler filtering, bore-sight error, NCI(Non-Coherent Integration), CFAR(Constant False Alarm Rate) and etc.