• Proceedings of the KAIS Fall Conference
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• 2005.05a
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• pp.169-172
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• 2005

반도체 기술의 발달과 더불어 디지털 신호 기억회로는 매우 빠른 속도로 발달되었다. 그러나 수 GHz 이상의 높은 고주파 신호를 저장하였다가 복재하는 것은 매우 어려운 기술이다. 고주파 신호의 복재를 위해서 과거에는 신호 감쇄가 적은 고주파 케이블을 일정한 길이로 감아서 시간지연을 시키는 아날로그 방식의 고주파 신호 저장회로가 사용되었으나, 신호 샘플링 및 광대역 신호 변환기 등이 발전되면서 고주파 신호를 고속으로 샘플링 한 뒤 디지털 회로에 저장 한 후에 필요시 고주파 신호를 복재하는 기술이 가능해 쳐다. 본 논문에서는 주파수 대역이 3 옥타브 이상 되는 광대역 고주파 신호를 저장하고 복재할 때 샘플링 주파수에 따른 특성을 분석하였다.

• The Journal of the Acoustical Society of Korea
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• v.37 no.5
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• pp.271-275
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• 2018

There are several methods for estimating the time delay between incoming signals to two sensors. Among them, the GCC-PHAT (Generalized Cross Correlation-Phase Transform) method, which estimates the relative delay from the signal whitening and the cross-correlation between the different signal inputs to the two sensors, is a traditionally well known method for achieving stable performance. In this paper, we have identified a part of GCC-PHAT that can improve the periodicity. Also, we apply the auto-correlation method that is widely used as a method to improve the periodicity. Comparing the proposed method with the GCC-PHAT method, we show that the proposed method improves the mean square error performance by 5 dB ~ 15 dB at the SNR above 0 dB for white Gaussian signal source and also show that the method improves the mean square error performance up to 15 dB at the SNR above 2 dB for the color signal source.

• Journal of the Institute of Convergence Signal Processing
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• v.2 no.4
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• pp.71-76
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• 2001

In this paper we propose the Digital Automatic Gain Controller for IEEE 802.11a-High-speed Physical Layer in the 5 GHz Band. The input gain it estimated by calculating the energy of the training symbol that it a synchronizing signal. The renewal gain is calculated by comparing the estimated gain with the ideal gain. The renewal gain is converted into the controlled voltage for GCA to reduce or amplify the input signals. We used a piecewise-linear approximation to reduce the hardware size. The gain control is performed seven times to provide more accurate gain control. The proposed automatic gain controller is designed with VHDL and verified by using the Xilinx FPGA.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.8 no.5
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• pp.1120-1128
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• 2004

In this paper, we has designed and implemented Up-converter for K-band with high IMD3 performance using balanced power amplifier. It is consisted of PA module and, Local Oscillator module with reject Filter, mixer module and If block, and Up-converter has a local loop path to decide whether it operate or not and has the sensing port to inspect output power level. According to the power budget of designed Up-converter, K-band balanced power amplifier was fabricated by commercial MMIC. Measurement results of up-converter show about 40dB Gain, PldB of 29dBm and OIP3 was 38.25dBm, that is good performance compared to power budgets. We has adjusted gate voltage of MMIC to control more than 30 dB gain. This up-converter was used in transceiver for PTP and PTMP, and applied to digital communication system that use QAM and QPSK modulation.

• Journal of IKEEE
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• v.24 no.3
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• pp.853-858
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• 2020

This paper proposes a 2-ch DC-DC converter for OLED display with immunity against RF noise inserted from communication device. For RF signal immunity, an input voltage variation reduction circuit that attenuates as much as the input voltage variation is embedded. The boost converter for positive voltage V_POS operates in SPWM-PWM dual mode and has a dead time controller to increase power efficiency. The inverting charge pump for negative voltage V_NEG is a 2-phase scheme and operates in PFM using VCO to reduce output ripple voltage. Simulation results using 0.18 ㎛ BCDMOS process show that the overshoot and undershoot of the output voltage decrease from 10 mV to 2 mV and 5 mV, respectively. The 2-ch DC-DC converter has power efficiency of 39%~93%, and the power efficiency of the boost converter is up to 3% higher than the conventional method without dead time controller.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.35C no.10
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• pp.22-29
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• 1998

In this paper, an 10 bit current-mode CMOS A/D converter with a current predictor is designed with a CMOS process to be integrated into a portable image signal processing system. A current predictor let the number of comparator reduce to 70 percent compared with the two step flash architecture. The current magnitude of current reference is reduced to 68 percent with a modular current reference. The designed 10 bit Low-power current-mode CMOS A/D converter with a current predictor is simulated with HSPICE using 0.6$\mu\textrm{m}$ N-well single-poly triple-metal CMOS process parameters. It results in a conversion rate of 10MSamples/s. A power consumption is measured to be 94.4mW at single +5V supply voltage. The 10 bit A/D converter fabricated using the same process occupies the chip area of 1.8mm x 2.4mm.

• Journal of Satellite, Information and Communications
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• v.8 no.2
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• pp.88-93
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• 2013

The wideband chirp signal generator to enhance the resolution of synthetic aperture radar of obtaining the earth observation image is needed. This paper deals with designing, manufacturing and testing the wideband digital chirp signal generator having high resolution for LEO earth observation satellite. The wideband digital chirp signal generator is implemented with the memory-map based structure which is mostly applied in the satellite, and consists of the digital module to generate the digital chirp signal and the RF module to perform the quadrature modulation. The I/Q signals stored in the memory of the digital module are D/A converted and delivered to be quadrature modulated with the reference signal of 1275 MHz in the RF module. Furthermore, the test bench and GUI to validate the signal generator function are also developed. It is found that the requirement of 144 MHz bandwidth for the digital chirp signal generator is well met. Finally it is noteworthy that the distortion occurred in the chirp signal generator was compensated by the pre-distortion compensation.

• Proceedings of the Acoustical Society of Korea Conference
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• spring
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• pp.183-186
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• 2004

본 논문에서는 수중 초음파 통신용 QPSK 버스트 수신기를 DSP시스템을 이용하여 구현하기위한 시스템 설계에 대하여 논한다. 본 논문에서 고려하는 시스템은 25kHz의 반송주파수를 사용하고, 심벌율은 5kHz이며, 데이터 전송율은 10,000bps이다. 송신기에서 심벌정보를 전송하기 위해 펄스성형필터를 거친 신호를 디지털 믹서기를 이용하여 디지털 영역에서 반송주파수 대역으로 신호를 변조한 후 200kHz로 샘플링하는 D/A변환기를 이용하여 전송 아날로그 신호를 생성한다. 수신기에서는 수신 신호를 디지털로 처리하기 위하여 100kHz로 free running하는 A/D 변환기를 이용하여 수신 데이터를 얻는다. 수신기에서는 32심벌 길이의 프리앰블을 이용하여 프레임 동기를 찾음과 동시에 개략적인 심벌시간 동기와 위상편이를 추정한다. 추정한 위상편이값은 2차 PLL (phase-looked loop)의 초기값으로 사용하여 위상 추적을 수행하는 전송 시스템이다. 또한, 된 논문에서는 실해역 전송 시험 테이터를 통하여 조류의 변화에 의해 발생하는 Doppler 편이를 보상하기 위하여 PLL이 필수적으로 필요함을 보인다.

• Proceedings of the KIEE Conference
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• summer
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• pp.956-958
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• 2004

이 논문에서, 우리는 PMLSM(permanent magnet linear synchronous motor) 시스템에서 발생하는 detent force의 ripple 저감을 위한 진동보상 모델과 제안한 구조에 대한 제어기 설계 방법을 제시한다. 본 논문에서 고려되어진 제어기는 feedforward 보상기, PID feedback 보상기, 그리고 adaptive feedforward 보상기의 세 부분으로 구성된 제어기를 사용한다. 특히, PMLSM의 위치 정밀성 향상에 관한 연구를 위한 정밀 위치 제어의 문제는 PM으로 인해 발생하는 detent force이며, 이를 해결하기 위해 출력신호를 웨이블릿 변환하여 추출 후 이를 보상하였다.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.48 no.6
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• pp.34-40
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• 2011

From the present paper researched about the Design of Image Rejection SSB Modulator for X-Band Monopulse RADAR using Waveguide Hybrid Coupler. Generally, SSB modulator mixes IF(RF) and LO signals, and then it converts to RF(IF) frequency band. In this case, in order to transmit one sideband from RF band, SSB modulator is demanded the removal of image and LO signal. The balanced mixer was designed using waveguide hybrid coupler and crystal mixer diode to mix LO and IF signal. And also the IF Amplifier was designed for IF(+) and IF(-) signal generation which have $90^{\circ}$ phase differences which are suitable in two crystal mixer diode inputs. In order to maintain a high electric reliability from high frequency band the waveguide and IF amplifier's case were manufactured with aluminum using deep brazing techniques. The test result of SSB modulator, LO and sideband signal rejection ratio were 14.2dB and 18.5dB respectively.