• Journal of the Institute of Electronics Engineers of Korea CI
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• v.42 no.6
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• pp.101-108
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• 2005

In this paper, we proposed a new algorithm of pulse generation and detection for the UWB multimedia communication system. The existing UWB systems using Gaussian pulse have some difficulties to cope with bandwidth limitation and frequency transition. In this paper, we introduce a new pulse generation method, which is able to control the bandwidth and center frequency that applies to the frequency modulation method, thus the proposed algorithm could improve the detection performance of receiving. And we proposed the multi channel transmission algorithm which transmits 1 channel synthesized at same time using the wavelet synthesis filter. Because of wavelet filter's perfect reconstruction property, the BER(Bit Error Rate) of transmission data is not changed by the number of accessed user. BER is changed only the property of channel transmission. By the results of simulation, when shift SNR from 2dB to 8dB on AWGN channel, we confirmed that the proposed algerian has $3.9063{\times}10^{-4}$ BER at 4dB SNR(AWGN channel).

• The KIPS Transactions:PartA
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• v.11A no.2
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• pp.129-142
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• 2004

As the Internet gets faster, the demand for high-speed routers that are capable of forwarding more than giga bits of data per second keeps increasing. In the previous research, Bitmap Trie algorithm was developed to rapidly execute LPM(longest prefix matching) process which is Well known as the Severe performance bottleneck. In this paper, we introduce a novel algorithm that drastically enhanced the performance of Bitmap. Trie algorithm by applying three techniques. First, a new table called the Count Table was devised. Owing to this table, we successfully eliminated shift operations that was the main cause of performance degradation in Bitmap Trie algorithm. Second, memory utilization was improved by removing redundant forwarding information from the Transfer Table. Lastly. the range of prefix lookup was diversified to optimize data accesses. On the other hand, the processing delays were classified into three categories according to their causes. They were, then, measured through the execution-driven simulation that provides the higher quality of the results than any other simulation techniques. We tried to assure the reliability of the experimental results by comparing with those that collected from the real system. Finally the Enhanced Bitmap Trie algorithm reduced 82% of time spent in previous algorithm.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.34 no.9C
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• pp.906-914
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• 2009

SC-FDMA is employed in the 3GPP-LTE standard as the uplink transmission scheme. SC-FDMA has advantages that the signal has a low PAPR property and a simple equalizer such as FD-LE can be implemented. But FD-LE has inferior performance to Hybrid-DFE composed of frequency-domain feedforward filter and time-domain feedback filter. Recently, several IB-DFE algorithms have been proposed to overcome the disadvantages of implementation and processing complexity of Hybrid-DFE and to obtain superior performance to FD-LE. In this paper, we apply several IB-DFE algorithms to 3GPP-LTE uplink system and compare their performance by calculating BER. We investigate the effects of channel estimation errors and Doppler shift on performance. Finally, by analyzing computational complexity of IB-DFEs, we present some criteria to choose appropriate algorithm and to decide the number of iterative processes.

• KIPS Transactions on Software and Data Engineering
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• v.3 no.9
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• pp.375-380
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• 2014

Under controlled environment, such as fixed viewpoints or consistent illumination, the performance of face recognition is usually high enough to be acceptable nowadays. Face recognition is, however, a still challenging task in real world. SIFT(Scale Invariant Feature Transformation) algorithm is scale and rotation invariant, which is powerful only in the case of small viewpoint changes. However, it often fails when viewpoint of faces changes in wide range. In this paper, we use Affine SIFT (Scale Invariant Feature Transformation; ASIFT) to detect affine invariant local descriptors for face recognition under wide viewpoint changes. The ASIFT is an extension of SIFT algorithm to solve this weakness. In our scheme, ASIFT is applied only to gallery face, while SIFT algorithm is applied to probe face. ASIFT generates a series of different viewpoints using affine transformation. Therefore, the ASIFT allows viewpoint differences between gallery face and probe face. Experiment results showed our framework achieved higher recognition accuracy than the original SIFT algorithm on FERET database.

• Journal of Digital Contents Society
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• v.19 no.2
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• pp.371-376
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• 2018

In the system security technology, the information hiding field is developed as technologies for embedding information, which are generally used as contents media. The proposed technique is a technical steganography technique which uses a technique of concealing certain information through physical / statistical change of signal values of contents. Recently, there have been various studies based on histogram shifting in reversible data concealment. In multi - peak histogram shifting, the capacity of data concealment gradually increased by applying multiple peak histogram method. In this paper, we analyze the effect of concealment in terms of adopting the histogram shift method including skipping. In addition, we propose multi - branch data concealment as a general method to improve concealment capacity. The above proposal has proved to be an example using mathematical expressions, and further improvement measures could be derived.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.27 no.6C
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• pp.632-639
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• 2002

To reduce the area and power consumption in constant coefficient multiplications, the constant coefficient can be encoded using canonic signed digit(CSD) representation. When the partial product terms are added depending on the nonzero bit(1 or -1) positions in the CSD-encoded multiplier, all sign bits are properly extended before the addition takes place. In this paper, to reduce the overhead due to sign extension, a new method is proposed based on the fact that carry propagation in the sign extension part can be controlled such that a desired input bit can be propagated as a carry. Also, a fixed-width multiplier design method suitable for CSD multiplication is proposed. As an application, 43-tap filbert transformer for SSB/BPSK-DS/CDMA is implemented. It is shown that, about 16∼28% adders can be saved by the proposed method compared with the conventional methods.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.41 no.2
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• pp.163-171
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• 2016

In order to detect the exact position of high-speed train, it is necessary to obtain location information from the transponder tag installed along the track. In this paper, we proposed parallel descrambling scheme for high-speed railway transponder system, which aims for reducing the processing time required to decode telegram. Since a telegram is stored in a tag after information bits are scrambled by an encoder, decoding procedure includes descrambling of received telegram to recover the original information bits. By analyzing the structure of the descrambling shift register circuit, we proposed a parallel descrambling scheme for fast decoding of telegram. By comparing the required number of clocks, it is shown that the proposed scheme significantly outperforms the original one.

• Journal of the Institute of Convergence Signal Processing
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• v.5 no.3
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• pp.230-235
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• 2004

This paper describes FPGA implementation of a pointer interpreter which can support a synchronization of SDH(or SONET)-based transmission network. The pointer interpreter consists of a pointer-word extractor and a pointer-word interpreter The pointer-word extractor which is composed of mod-6480 counter, shift register and pointer synchronizing block, finds out the H1 and H2 pointer word from a 51.84 Mb/s AU-3/STS-1 data frame and then performs the synchronizing with a 6.48 Mb/s by dividing them in 8. Based on the extracted pointer word, pointer-word interpreter analyzes pointer states such LOP, AIS and NORM according to pointer state-transition algorithm. It consists of a majority vote, a pointer word valid/invalid check, a pointer justification, and a pointer state check. The simulation results of Xilinx Virtex XCV200PQ240 FPGA chip shows the exact pointer word extraction and correct decision of pointer status based on extracted pointer word. The proposed pointer interpreter is suitable for pointer interpretation of 155 Mb/s STM-1/STS-3 frame.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.22 no.3
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• pp.434-442
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• 2018

In this paper, we propose a road lane color recognition method from the image obtained from a driving vehicle. In autonomous vehicle techniques, lane information becomes more important as the level of autonomous driving such as lane departure warning and dynamic lane keeping assistance is increased. In particular the lane color recognition, especially the white and the yellow lanes, is necessary technique because it is directly related to traffic accidents. In this paper, color information of lane and road area is mapped to a 2-dimensional S-color space based on lane detection. And the center of the feature distribution is obtained by using an improved mean-shift algorithm in the S-color space. The lane color is determined by using the distance between the center coordinates of the color features of the left and right lanes and the road area. In various illumination conditions, about 97% color recognition rate is achieved.

• Journal of the Korea Society of Computer and Information
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• v.15 no.1
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• pp.13-21
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• 2010

IEEE 1149.1 test architecture was proposed to support the test of elements within the boards. It is a large serial shift register that uses the TDI pin as an input and the TDO pin as an output. Even though it performs the board level test perfectly, there is a problems of running system level test when the boards are equipped to the system. To test real time operation signal on test pin, output speed of serial shift register chain must be above double clock speed of shift register. In this paper, we designed a runtime test architecture and a runtime test procedure under running system environments to capture runtime signal at system clock rate. The suggested runtime test architecture are simulated by Altera Max+Plus 10.0. through the runtime test procedure. The simulation results show that operations of the suggested runtime test architecture are very accurate.