• Korean Journal of Optics and Photonics
• /
• v.5 no.3
• /
• pp.423-430
• /
• 1994

We designed and fabricated the single mode fiber pigtailed DFB-LD module for 2.5 Gbps optical communication system. In the design of the DFB-LD module, we made the module divided into two parts of inner sub-module and outer 14-pin butterfly package and cylindrical shaped sub-module contain quasi confocal 2 lens system including optical isolator and electrical connection between these parts via hybrid substrate of bias T circuit. Laser welding was used to assemble the sub-module which requires accurate fixing between optical elements. The fabricated DFB-LD module showed optical coupling efficiency of 20% and - 3 dB small signal response of more than 2.6 GHz. We confirmed mechanical reliability of the module by temperature cycle test where the tested module exhibit optical power fluctuation of less than 10%. Finally we evaluated the performance of the fabricated DFB-LD module as light source of 2.5 Gbps optical communication system, sensitivity of - 30.2 dBm was obtained through 47 km optical fiber transmission under the criterion of $1\times10^{-10}$ BER and transmission penalties were 1.5 dB caused by extinction ratio and 1.0 dB caused by chromatic dispersion of normal single mode fiber. fiber.

• Journal of the Korea Academia-Industrial cooperation Society
• /
• v.20 no.4
• /
• pp.639-647
• /
• 2019

Recently, as the semiconductor integration technology due to miniaturization and high density of electronic equipment have developed, it is importantly recognized the application of thermal control system in order to release inner heat generated from chips, modules, In this study, we considered the heat transfer and pressure drop characteristics in a horizontal channel with four blocks using k-${\omega}$ SST turbulence model During CFD (Computational Fluid Dynamics) analysis, the parameters applied block width, block height, heat source and turbulence generator placement etc. As the boundary conditions of analysis, the channel inlet temperature and flow velocity were respectively 300 K and 3.84 m/s, the heat flux was $358W/m^2$. As a result, the heat transfer performance was decreased as the block width ratio (w/h) was increased, while it was increased as the block height ratio (h/w) was increased. In addition, as the arrangement of heat source size was increased to high heat flux from low heat flux, it was influenced by heat source size and the heat transfer coefficient showed a tendency to increase, When the turbulence generator was installed in the upper part of block No. 1 position the closely to the channel entrance, the heat transfer characteristics was greatly influenced on the whole of four heating blocks. and in oder to consider the pressure drop characteristics, we are able to select the most appropriate turbulence generator's position.

• Journal of the Institute of Electronics and Information Engineers
• /
• v.50 no.7
• /
• pp.122-130
• /
• 2013

This work proposes a 12b 100MS/s 45nm CMOS four-step pipeline ADC for high-speed digital communication systems requiring high resolution, low power, and small size. The input SHA employs a gate-bootstrapping circuit to sample wide-band input signals with an accuracy of 12 bits or more. The input SHA and MDACs adopt two-stage op-amps with a gain-boosting technique to achieve the required DC gain and high signal swing range. In addition, cascode and Miller frequency-compensation techniques are selectively used for wide bandwidth and stable signal settling. The cascode current mirror minimizes current mismatch by channel length modulation and supply variation. The finger width of current mirrors and amplifiers is laid out in the same size to reduce device mismatch. The proposed supply- and temperature-insensitive current and voltage references are implemented on chip with optional off-chip reference voltages for various system applications. The prototype ADC in a 45nm CMOS demonstrates the measured DNL and INL within 0.88LSB and 1.46LSB, respectively. The ADC shows a maximum SNDR of 61.0dB and a maximum SFDR of 74.9dB at 100MS/s, respectively. The ADC with an active die area of $0.43mm^2$ consumes 29.8mW at 100MS/s and a 1.1V supply.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.46 no.1
• /
• pp.98-106
• /
• 2009

This work proposes a 1280-RGB $\times$ 800-Dot 70.78mW 0.l3um CMOS LCD driver IC (LDI) for high-performance 16M-color low temperature poly silicon (LTPS) thin film transistor liquid crystal display (TFT-LCD) systems such as ultra mobile PC (UMPC) and mobile applications simultaneously requiring high resolution, low power, and small size at high speed. The proposed LDI optimizes power consumption and chip area at high resolution based on a resistor-string based architecture. The single column driver employing a 1:12 MUX architecture drives 12 channels simultaneously to minimize chip area. The implemented class-AB amplifier achieves a rail-to-rail operation with high gain and low power while minimizing the effect of offset and output deviations for high definition. The supply- and temperature-insensitive current reference is implemented on chip with a small number of MOS transistors. A slew enhancement technique applicable to next-generation source drivers, not implemented on this prototype chip, is proposed to reduce power consumption further. The prototype LDI implemented in a 0.13um CMOS technology demonstrates a measured settling time of source driver amplifiers within 1.016us and 1.072us during high-to-low and low-to-high transitions, respectively. The output voltage of source drivers shows a maximum deviation of 11mV. The LDI with an active die area of $12,203um{\times}1500um$ consumes 70.78mW at 1.5V/5.5V.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.43 no.11 s.353
• /
• pp.58-68
• /
• 2006

This work proposes a 10b 250MS/s $1.8mm^2$ 85mW 0.13um CMOS A/D Converter (ADC) for high-performance integrated systems such as next-generation DTV and WLAN simultaneously requiring low voltage, low power, and small area at high speed. The proposed 3-stage pipeline ADC minimizes chip area and power dissipation at the target resolution and sampling rate. The input SHA maintains 10b resolution with either gate-bootstrapped sampling switches or nominal CMOS sampling switches. The SHA and two MDACs based on a conventional 2-stage amplifier employ optimized trans-conductance ratios of two amplifier stages to achieve the required DC gain, bandwidth, and phase margin. The proposed signal insensitive 3-D fully symmetric capacitor layout reduces the device mismatch of two MDACs. The low-noise on-chip current and voltage references can choose optional off-chip voltage references. The prototype ADC is implemented in a 0.13um 1P8M CMOS process. The measured DNL and INL are within 0.24LSB and 0.35LSB while the ADC shows a maximum SNDR of 54dB and 48dB and a maximum SFDR of 67dB and 61dB at 200MS/s and 250MS/s, respectively. The ADC with an active die area of $1.8mm^2$ consumes 85mW at 250MS/s at a 1.2V supply.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.43 no.11 s.353
• /
• pp.37-47
• /
• 2006

This work proposes a 10b 25MS/s $0.8mm^2$ 4.8mW 0.13um CMOS A/D Converter (ADC) for high-performance wireless communication systems such as DVB, DAB and DMB simultaneously requiring low voltage, low power, and small area. A two-stage pipeline architecture minimizes the overall chip area and power dissipation of the proposed ADC at the target resolution and sampling rate while switched-bias power reduction techniques reduce the power consumption of analog amplifiers. A low-power sample-and-hold amplifier maintains 10b resolution for input frequencies up to 60MHz based on a single-stage amplifier and nominal CMOS sampling switches using low threshold-voltage transistors. A signal insensitive 3-D fully symmetric layout reduces the capacitor and device mismatch of a multiplying D/A converter while low-noise reference currents and voltages are implemented on chip with optional off-chip voltage references. The employed down-sampling clock signal selects the sampling rate of 25MS/s or 10MS/s with a reduced power depending on applications. The prototype ADC in a 0.13um 1P8M CMOS technology demonstrates the measured DNL and INL within 0.42LSB and 0.91LSB and shows a maximum SNDR and SFDR of 56dB and 65dB at all sampling frequencies up to 2SMS/s, respectively. The ADC with an active die area if $0.8mm^2$ consumes 4.8mW at 25MS/s and 2.4mW at 10MS/s at a 1.2V supply.