• Journal of KIISE:Computer Systems and Theory
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• v.29 no.7
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• pp.422-430
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• 2002

For a time-multiplexed FPGA, a circuit is partitioned into several subcircuits, so that they temporally share the same physical FPGA device by hardware reconfiguration. In these architectures, all the hardware reconfiguration information called contexts are generated and downloaded into the chip, and then the pre-scheduled context switches occur properly and timely. Since the maximum number of the LUT's required in the same time determines the size of the chip used in the synthesis, it needs to be minimized, if possible. Many previous work use their own approaches, which are very similar to either scheduling method in high level synthesis or multi-way circuit partitioning method, to solve the problem. In this paper, we propose a method which estimates the lower bound on the number of LUT's without performing any actual synthesis. The estimated lower bounds help to evaluate the results of the previous work. If the estimated lower bound on the number of LUT's exactly matches the number of LUT's of the result from the previous work, the result must be optimal. In contrast, if they do not match, the following two cases are expected : the more exact lower bound may exist, or we might find the new synthesis result better than the result from the previous work. Experimental results show that our lower bound estimation method is very accurate. In almost al] cases experimented, the estimated lower bounds on the number of LUT's exactly match those of the previous synthesis results respectively, implying that the best results from the previous work are optimal as well as our method predicted the exact lower bound for those examples.

• Journal of the Korean Society for Aeronautical & Space Sciences
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• v.40 no.5
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• pp.454-460
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• 2012

DTC(Data Terminal Controller) for UAV has been developed using FPGA. It provides the functions of Error Correction and Time-division Mux/Demux for stable data-link. RTOS VxWorks also has been used for real-time control of data-link. FPGA Design of DTC facilitates the modification and extension of various I/O device, and VxWorks ensures real-time availability of data-link control and provides flexibilities of changes of S/W design. The DTC is expected to be deployed easily for various UAV systems.

• Journal of KIISE:Computer Systems and Theory
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• v.30 no.9
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• pp.512-522
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• 2003

For a time-multiplexed FPGA, a circuit is partitioned into several subcircuits, so that they temporally share the same physical FPGA device by hardware reconfiguration. In these architectures, all the hardware reconfiguration information called contexts are generated and downloaded into the chip, and then the pre-scheduled context switches occur properly and timely. Typically, the size of the chip required to implement the circuit depends on both the maximum number of the LUT blocks required to implement the function of each subcircuit and the maximum number of micro-registers to store results over context switches in the same time. Therefore, many partitioning or synthesis methods try to minimize these two factors. In this paper, we present a new estimation technique to find the lower bound on the number of micro-registers which can be obtained by any synthesis methods, respectively, without performing any actual synthesis and/or design space exploration. The lower bound estimation is very important in sense that it greatly helps to evaluate the results of the previous work and even the future work. If the estimated lower bound exactly matches the actual number in the actual design result, we can say that the result is guaranteed to be optimal. In contrast, if they do not match, the following two cases are expected: we might estimate a better (more exact) lower bound or we find a new synthesis result better than those of the previous work. Our experimental results show that there are some differences between the numbers of micro-registers and our estimated lower bounds. One reason for these differences seems that our estimation tries to estimate the result with the minimum micro-registers among all the possible candidates, regardless of usage of other resources such as LUTs, while the previous work takes into account both LUTs and micro-registers. In addition, it implies that our method may have some limitation on exact estimation due to the complexity of the problem itself in sense that it is much more complicated than LUT estimation and thus needs more improvement, and/or there may exist some other synthesis results better than those of the previous work.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.37 no.2
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• pp.65-77
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• 2000

We propose a new formulation by quadratic boolean programming to partition circuits for FPGA based reconfigurable circuit boards, in which the routing topology among IC chips are predetermined. The formulation is to minimize the sum of the wire length by considering the nets passing through IC chips for the interconnections between chips which are not adjacent, in addition to the constraints considered by the previous partition methods. We also describe a heuristic method, which consist of module assignment method to efficiently solve the problem. Experimental results show that our method generates the partitions in which the given constraints are all satisfied for all the benchmark circuits tested. The pin utilization are reduced for the most of the circuits and the total wire length of the routed nets are improved up to 34.7% compared to the previous method.

• Proceedings of the Acoustical Society of Korea Conference
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• spring
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• pp.343-346
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• 2000

This paper presents a filter bank designed for the multi-channel audio equalizer. A time-shared multiplier is also proposed to implement the equalizer with a minimum number of gates when it is synthesized with ASIC or FPGA. Further reduction of the number of required gates is achieved by designing the multiplier based on a cascaded sequential circuit utilizing partial multiplications. The equalizer is realized with FPGA and its real-time operation verifies the reliability and high fidelity of the designed system.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.17 no.3
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• pp.166-175
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• 2024

In this paper, the Window-Masking Method and HAT (Hardware Attached Top) CPU SoM (System on Module) are used to improve the performance and reduce the weight of the MANET (Mobile Ad-hoc Network) network synchronization system using time division redundancy. We propose converting it into a RISC-V based soft-core MCU and mounting it on an FPGA, a hardware accelerator. It was also verified through experiment. In terms of performance, by applying the proposed technique, the synchronization acquisition range is from -50dBm to +10dBm to -60dBm to +10dBm, the lowest input level for synchronization is increased by 20% from -50dBm to -60dBm, and the detection delay (Latency) is 220ns. Reduced by 43% to 125ns. In terms of weight reduction, computing resources (48%), size (33%), and weight (27%) were reduced by an average of 36% by replacing with soft-core MCU.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.35C no.11
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• pp.1-10
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• 1998

The advent of deep submicron technologies in the age of portable electronic systems creates a moving target for CAB algorithms, which now need to reduce power as well as delay and area in the existing design methodology. This paper presents a resynthesis algorithm for logic decomposition on mapped circuits. The existing algorithm uses a Huffman encoding, but does not consider glitches and effects on logic depth. The proposed algorithm is to generalize the Huffman encoding algorithm to minimize the switching activity of non-critical subcircuits and to preserve a given logic depth. We show how to obtain a transition-optimum binary tree decomposition for AND tree with zero gate delay. The algorithm is tested using SIS (logic synthesizer) and Level-Map (LUT-based FPGA lower power technology mapper) and shows 58%, 8% reductions on power consumptions, respectively.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.9 no.3
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• pp.587-594
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• 2005

In the paper, after we propose a viterbi decoder which has multiple buffering and parallel processing decoding scheme through expanding time-divided imput signal, and map a FPGA, we implement a channel coding system together with PC-based software. Continuous input signal is buffered as order of decoding length and is parallel decoded using a high speed cell for viterbi decoding. Output data rate increases linearly with the cell formed the viterbi decoder, and flexible operation can be satisfied by programming controller and modifying input buffer. The tell for viterbi decoder consists of HD block for calculating hamming distance, CM block for calculating value in each state, TB block for trace-back operation, and LIFO. The implemented cell of viterbi decoder used 351 LAB(Logic Arrary Block) and stably operated in maximum 139MHz in APEX20KC EP20K600CB652-7 FPGA of ALTERA. The whole viterbi decoder including viterbi decoding cells, input/output buffers, and a controller occupied the hardware resource of $23\%$ and has the output data rate of 1Gbps.

• Journal of IKEEE
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• v.8 no.1 s.14
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• pp.128-135
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• 2004

This paper proposes a phase measurement algorithm which is based on the recursive implementation of sliding-DFT. The algorithm is designed to have a robust behavior against the erroneous factors of frequency drift, additive noise, and twiddle factor approximation. The size of phase error caused by the finite wordlength implementation of DFT twiddle factors is shown significantly lower than that of magnitude error. The drastic reduction of the phase error is achieved by the exploitation of the quadruplet symmetry characteristics of the approximated twiddle factors in the complex plane. Four channel power-line phase measurement system is also designed and implemented based on the time-multiplexed sharing architecture of the proposed algorithm. The operation of the developed system is also verified by the experiment performed under the test environment implemented with the multi-channel function generator and the on-line interfaced host processor system. The proposed algorithm's features of phase measurement accuracy and its robustness against the finite wordlength effects can provide a significant impact especially for the ASIC or microprocessor based embedded system applications where the enhanced processing speed and implementation simplicity are crucial design considerations.

• Proceedings of the KIEE Conference
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• 2005.10b
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• pp.436-438
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• 2005

본 논문에서는 전력선 위상 측정을 위해 A/D 변환기 및 위상계측 연산장치를 집적한 하이브리드 센서칩의 구현 기법을 제시하였다. 개발한 위상계측 연산장치는 recursive sliding-DFT에 기반하였으며 곱셈기의 시분할 공유 구조를 사용하여 칩의 구현 면적을 최소화 하였다. 60Hz의 전력선 신호를 중심주파수로 하는 AD 변환장치는 sigma-delta ADC를 기반으로 하여 8-bit 정밀도를 제공하며 아날로그부의 구현을 최소화하도륵 설계하였다. 설계한 하이브리드 센서칩은 컴퓨터 시뮬레이션 및 FPGA 구현을 통해 동작을 검증하였으며, 검증 완료후 $0.35{\mu}m$ CMOS 공정기술로 구현하였다. 전력선 위상을 측정하기 위해 구현된 4채널 하이브리드 센서 칩의 설계면적은 $5{\times}5m^2$ 의 약 20%정도를 차지하였다.