• The Journal of the Korea institute of electronic communication sciences
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• v.8 no.9
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• pp.1285-1291
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• 2013

In this paper, a double circular ring monopole antenna for wideband applications is designed and fabricated. The proposed antenna is based on a planar monopole design, and composed of double circular ring of radiating patches and ground plane to obtain the wideband characteristics. To get the optimized parameters, we used the simulator, Ansoft's High Frequency Structure Simulator(HFSS) and found the parameters that effect antenna characteristics. Using the obtained parameters, the proposed antenna is fabricated. The fabricated antenna is measured at the operating frequencies, and the return loss coefficient, gain, and radiation patterns are determined. The results of measurement, -10dB impedance bandwidth, measured return loss is 4,530 MHz(2,510-7,040 MHz) and antenna peak and average gains for the frequencies are obtained 0.71~3.38 dBi, -3.85~0.3 dBi, respectively. In case of radiation patterns, the proposed antenna displays nearly omnidirectional radiation characteristics in the E-plane, and monopole-like radiation pattern characteristics in the H-plane.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.15 no.1
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• pp.90-97
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• 2001

A high frequency resonant inverter consisting of iliree unit Half-Bridge serial resommt inverter used as power source of induction heatmg at high frequency is presented in this paper. As a output [Dwer control strategy, sequencial time-sharing gate contml methcd is applied. This methcd is TDM(Time Division Multiplexing), which is broadly used with digital and analog signals transmission in communication system 1be analysis of the proposed circuit is generally described by using the normalized pararmenters. Also, the principle of basic operating and the its characteristics are estimated by the parameters such as switching frequency, load resistance. Also, according to the calculated characteristics value, a method of the circuit design and operating characteristics of the inverter is proposed. This paper proves the validity of theoretical analysis through the Pspice. This proposed inverter show that it can be practically used in future as power source system for induction heating application, DC-DC converter etc. r etc.

• Journal of KIISE:Computing Practices and Letters
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• v.8 no.3
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• pp.261-267
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• 2002

In SOC(System On a Chip) designs, reducing time and cast for design verification is the most critical to improve the design productivity. this is mainly because the designs require co-verifying HW together with SW, which results in the increase of verification complexity drastically. In this paper, to cope with the verification crisis in SOC designs, we propose a new verification methodology, so called integrated co-verification, which lightly combine both co-simulation and co-emulation in unified and seamless way. We have applied our integrated co-verification to ARM/AMBA platform-based co-verification environment with a commercial co-verification tool, Seamless CVE, and a physical prototyping board. The experiments has shown clear advantage of the proposed technique over conventional ones.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.22 no.6
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• pp.14-17
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• 2008

This paper describes the simulation of a phase splitter for the design of Chireix Outphasing power amplifier. Phase splitter separate the input signal with $0[^{\circ}]$ into the signal with $+90[^{\circ}]$ and $-90[^{\circ}]$ Chireix Outphasing power amplifier get a linearized output from the signal amplifying and combining the separated signal with the phase of $+90[^{\circ}]$ and $-90[^{\circ}]$ of the phase splitter. phase splitter is the core device when designing Chireix Outphasing power amplifier. It is very difficult to design phase splitter with the difference of $90[^{\circ}]$. This phase splitter is used to design the difference of $180[^{\circ}]((90[^{\circ}]+{\alpha}),\;-(90[^{\circ}])+{\alpha}))$ using simulation tool and a differential amplifier.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.18 no.10
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• pp.2509-2515
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• 2014

In this paper, the conventional vertical structure for VLSI circuits CMOS intend to improve the stress effects of active region and built-in threshold voltage. For these improvement, the proposed structure is shallow trench isolation of moat shape. We want to analysis the electron concentration distribution, gate bias vs energy band, thermal stress and dielectric enhanced field of thermal damage between vertical structure and proposed moat shape. Physically based models are the ambient and stress bias conditions of TCAD tool. As an analysis results, shallow trench structure were intended to be electric functions of passive as device dimensions shrink, the electrical characteristics influence of proposed STI structures on the transistor applications become stronger the potential difference electric field and saturation threshold voltage, are decreased the stress effects of active region. The fabricated device of based on analysis results data were the almost same characteristics of simulation results data.

• Journal of the Institute of Convergence Signal Processing
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• v.10 no.2
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• pp.141-145
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• 2009

A C-to-SystemC synthesizer which processes the input behavior according to high-level synthesis, and then transforms the synthesis result into SystemC module code is implemented in this paper. In the synthesis process, the input behavioral description in C source code is scheduled using list scheduling algorithm and register allocation is performed using left-edge algorithm on the result of scheduling. In the SystemC process, the output from high-level synthesis process is transformed into SystemC module code by combining it with SystemC features such as channels and ports. The operation of the implemented C-to-SystemC synthesizer is validated through simulating the synthesis of elliptic wave filter in SystemC code. C-to-SystemC synthesizer can be used as a part of tool-chain which helps to implement SystemC design methodology covering from modeling to synthesis.

• Journal of the Korean Institute of Gas
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• v.17 no.5
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• pp.15-21
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• 2013

This study evaluated comparison of the risk according to the type of fuel by three-dimensional simulation tool(FLACS). The consequence analysis of fire explosion and jet-fire was carried out in the layout of a typical high-pressure gas filling stations using CNG, hydrogen and 30%HCNG. Under the same conditions, hydrogen had a 30kPa maximum overpressure, CNG had a 0.4kPa and HCNG had a 3.5kPa. HCNG overpressure was 7.75 times higher than the CNG measurement, but HCNG overpressure was only 11.7% compared to hydrogen. In case of flame propagation, hydrogen had a very fast propagation characteristics. On the other hand, CNG and HCNG flame propagation velocity and distance tended to be relatively safe in comparison to hydrogen. The estimated flame boundary distance by jet-fire of hydrogen was a 5.5m, CNG was a 3.4m and HCNG was a 3.9m.

• Proceedings of the Korean Vacuum Society Conference
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• 2010.02a
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• pp.459-459
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• 2010

대면적 마그네트론 스퍼터링 캐소드를 이용하여 고효율 스퍼터링을 실현하기 위해서는 진공 상태에서 하전입자의 손실을 최소화하여 플라즈마 내에 많은 입자를 구속하는 기술이 요구된다. 본 연구에서는 고효율 특성을 갖는 대면적 캐소드($127mm{\times}900mm$) 설계를 위해 유한요소법(Finite Element Method) 수치해석 알고리즘을 이용한 3차원 전자장(Magnetostatic) 시뮬레이션 툴을 이용하여 최적화된 캐소드를 설계하였다. 캐소드 타겟 배면에 생성되는 자기장의 3차원 특성 해석을 통해 타겟효율에 가장 큰 영향을 미치는 자속밀도의 관계를 분석하였다. 고효율 캐소드 구조 설계를 위해서는 타겟 배면에 평행한 자속밀도의 분포를 최대한 확보를 것이 매우 중요하다. 이러한 특성을 확보하기 위하여 캐소드 내부에 장착되는 자석 크기 및 특성에 따른 자속밀도 특성을 해석하였다. 개발된 마그네트론 캐소드에 Si 타겟을 장착하였다. 캐소드 특성 평가를 위해 Ar 분위기 및 $O_2$를 동시에 인가하여 Si 및 $SiO_2$ 박막을 유리기판에 코팅하였다. 코팅된 박막의 특성 평가는 결정구조와 두께에 따른 투과율 및 반사율 측정을 수행하였다. Si 박막의 경우, 갈색의 코팅막을 형성하였으며, $SiO_2$의 경우, 투명한 박막으로 증착되었고 조성분석(EDXS)에 의해 $SiO_2$로 잘 코팅되었음을 확인할 수 있었다. 그리고, $SiO_2$가 코팅된 막의 투과율은 유리기판에 비해 1% 정도 향상되었음을 확인할 수 있었다. 마그네트론 캐소드 성능은 Si 타겟의 erosion 형상 분석과 3차원 유한요소법 프로그램을 이용한 자기장 분석을 통해 비교 분석하였다.

• KIISE Transactions on Computing Practices
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• v.21 no.9
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• pp.587-595
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• 2015

Several fields of science have traditionally demanded large-scale workflow support, which requires thousands of central processing unit (CPU) cores. In order to support such large-scale scientific workflows, large-capacity cluster systems such as supercomputers are widely used. However, as users require a diversity of software packages and configurations, a system administrator has some trouble in making a service environment in real time. In this paper, we present a container-based cluster management platform and introduce an implementation case to minimize performance reduction and dynamically provide a distributed computing environment desired by users. This paper offers the following contributions. First, a container-based virtualization technology is assimilated with a resource and job management system to expand applicability to support large-scale scientific workflows. Second, an implementation case in which docker and HTCondor are interlocked is introduced. Lastly, docker and native performance comparison results using two widely known benchmark tools and Monte-Carlo simulation implemented using various programming languages are presented.

• KIPS Transactions on Computer and Communication Systems
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• v.8 no.11
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• pp.271-276
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• 2019

Conventional ARIA algorithm which is used LUT based-S-Box is fast the processing speed. However, the algorithm is hard to applied to small portable devices. This paper proposes the hardware design of optimized ARIA crypto-processor based on the modified composite field S-Box in order to decrease its hardware area. The Key scheduling in ARIA algorithm, both diffusion and substitution layers are repeatedly used in each round function. In this approach, an advanced key scheduling method is also presented of which two functions are merged into only one function for reducing hardware overhead in scheduling process. The designed ARIA crypto-processor is described in Verilog-HDL, and then a logic synthesis is also performed by using Xilinx ISE 14.7 tool with target the Xilnx FPGA XC3S1500 device. In order to verify the function of the crypto-processor, both logic and timing simulation are also performed by using simulator called ModelSim 10.4a.